CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 42

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

CP2200/1
9.7. De-Selecting Interrupt Sources
The power-fail (V
enabled after every device reset, regardless of the reset source. The RSTEN register can be used to prevent either
of these two reset sources from generating a device reset.
42
Table 13. Reset Electrical Characteristics
V
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
V
Minimum /RST Low Time to
Generate a System Reset
V
V
DD
Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.
Bit 2:
Bit 1:
Bit 0:
DD
DD
DD
= 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.
POR Threshold (VRST)
Monitor Turn-on Time
Monitor Supply Current
R/W
Bit7
—
ESWRST: Enable Software Reset
0: Software reset is not selected as a reset source.
1: Software reset is selected as a reset source.
EPFRST: Enable Power Fail Reset
0: The power fail detection circuitry (V
1: The power fail detection circuitry (V
UNUSED. Read = 0b, Write = don’t care.
Parameters
R/W
Bit6
—
DD
Monitor) reset is automatically enabled after every power-on reset. The software reset is
R/W
Bit5
Register 14. RSTEN: Reset Enable Register
—
R/W
Bit4
—
IOL = 8.5 mA
Conditions
DD
DD
R/W
Bit3
—
Rev. 1.0
Monitor) is not selected as a reset source.
Monitor) is selected as a reset source.
ESWRST EPFRST
R/W
Bit2
0.7 x V
Min
100
2.2
15
—
—
—
—
R/W
Bit1
DD
Typ
2.4
25
20
—
—
—
—
—
R/W
Bit0
—
0.3 x V
00000100
Reset Value
Address:
Max
0x72
0.6
2.6
50
50
—
—
—
DD
UNITS
µA
µs
µs
V
V
V
V