PCA9564BS,118 NXP Semiconductors, PCA9564BS,118 Datasheet - Page 5

• Manufacturer Part Number: PCA9564BS,118
• Description: IC CTRL PARALLEL/I2C BUS 20HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9564BS,118

• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Controller Type: Parallel Bus to I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Supply: 6mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: PCA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• High Level Output Current: - 7 mA
• Low Level Output Current: 8.5 mA
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Number Of Circuits: Single
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4001 - DEMO BOARD FOR PCA9564
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3405-2; 935272895118; PCA9564BS-T

Philips Semiconductors
FUNCTIONAL DESCRIPTION
General
The PCA9564 acts as an interface device between standard
high-speed parallel buses and the serial I
can act either as master or slave. Bidirectional data transfer between
the I
byte-wise basis, using either an interrupt or polled handshake.
Internal Oscillator
The PCA9564 contains an internal 9 MHz oscillator which is used
for all I
after ENSIO bit is set to “1”.
Registers
The PCA9564 contains four registers which are used to configure
the operation of the device as well as to send and receive serial data.
The registers are selected by setting pins A0 and A1 to the
appropriate logic levels before a read or write operation is executed.
CAUTION: Do not write to I
and the SIO is in master or addressed slave mode.
The Time-out Register, I2CTO: The time-out register is used to
determine the maximum time that SCL is allowed to be LOW before
the I
When the I
counter at every SCL transition.
The most significant bit of I2CTO (TE) is used as a time-out
enable/disable. A “1” will enable the time-out function. The time-out
period = (I2CTO[6:0] + 1)
some and is an approximate value.
The time-out register can be used in the following cases:
1. When the SIO, in the master mode, wants to send a START
2. In the master mode, the time-out feature starts every time the SCL
3. In case of a forced access to the I
2006 Sep 01
REGISTER
I2CTO
condition and the SCL line is held LOW by some other device.
The SIO waits a time period equivalent to the time-out value for
the SCL to be released. In case it is not released, the SIO
concludes that there is a bus error, loads 90H in the I2CSTA
register, generates an interrupt signal and releases the SCL and
SDA lines. After the microcontroller reads the status register, it
needs to send an external reset in order to reset the SIO.
goes LOW. If SCL stays LOW for a time period equal to or greater
than the time-out value, the SIO concludes there is a bus error
and behaves in the manner described above.
page 15.)
I2CCON
Parallel bus to I
I2CADR
I2CDAT
I2CSTA
NAME
I2CTO
2
2
C-bus and the parallel-bus microcontroller is carried out on a
C state machine is reset.
2
C timing. The oscillator requires up to 500 s to start-up
2
C interface is operating, I2CTO is loaded in the time-out
TE
7
Own address
REGISTER
FUNCTION
Time-out
TO6
Control
Status
Data
6
TO5
5
113.7 s. The time-out value may vary
2
2
C registers while the I
A1
C-bus controller
0
0
0
1
1
TO4
4
2
Time-out value
C-bus. (See more details on
A0
0
0
1
0
1
TO3
2
3
C-bus. On the I
WRITE
READ/
R/W
R/W
R/W
TO2
W
R
2
2
C-bus is busy
TO1
DEFAULT
1
2
C-bus, it
F8h
FFh
00h
00h
00h
TO0
0
5
The Address Register, I2CADR: I2CADR is not affected by the
SIO hardware. The contents of this register are irrelevant when SIO
is in a master mode. In the slave modes, the seven most significant
bits must be loaded with the microcontroller’s own slave address.
The most significant bit corresponds to the first bit received from the
I
HIGH level on the I
level on the bus. The least significant bit is not used but should be
programmed with a ‘0’.
The Data Register, I2CDAT: I2CDAT contains a byte of serial data
to be transmitted or a byte which has just been received. In master
mode, this includes the slave address that the master wants to send
out on the I
in the SD7 bit position and the Read/Write bit in the SD0 bit position.
The CPU can read from and write to this 8-bit register while it is not
in the process of shifting a byte. This occurs when SIO is in a
defined state and the serial interrupt flag is set. Data in I2CDAT
remains stable as long as SI is set. Whenever the SIO generates an
interrupt, the I2CDAT registers contain the data byte that was just
transferred on the I
NOTE: The I2CDAT register will capture the serial address as data
when addressed via the serial bus. Also, the data register will
continue to capture data from the serial bus during 38H so the
I2CDAT register will need to be reloaded when the bus becomes
free.
Eight bits to be transmitted or just received. A logic 1 in I2CDAT
corresponds to a HIGH level on the I
corresponds to a LOW level on the bus.
The Control Register, I2CCON: The microcontroller can read from
and write to this 8-bit register. Two bits are affected by the SIO
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the
I
the Serial Interrupt line to be de–asserted and the next clock pulse
on the SCL line to be generated. Since none of the registers should
be written to via the parallel interface once the Serial Interrupt line
has been de-asserted, all the other registers that need to be
modified should be written to before the content of the I2CCON
register is modified.
ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO
is in the “not addressed” slave state.
ENSIO = “1”: When ENSIO is “1”, SIO is enabled.
After the ENSIO bit is set, it takes 500 s for the internal oscillator to
start up, therefore, the PCA9564 will enter either the master or the
slave mode after this time. ENSIO should not be used to temporarily
2
2
C-bus after a start condition. A logic 1 in I2CADR corresponds to a
C-bus. A write to the I2CCON register clears the SI bit and causes
SD7 - SD0:
ENSIO
I2CADR
I2CCON
I2CDAT
, THE
2
C-bus, with the most significant bit of the slave address
BIT7
SD7
AA
SIO E
7
7
7
2
2
BIT6
C-bus, and a logic 0 corresponds to a LOW
C-bus.
SD6
NABLE
6
ENSIO
6
6
B
BIT5
SD5
5
IT
5
STA
own slave address
5
BIT4
SD4
4
4
2
STO
C-bus, and a logic 0
4
BIT3
SD3
3
3
SI
3
SD2
BIT2
PCA9564
CR2
2
Product data sheet
2
2
CR1
BIT1
SD1
1
1
1
0
SD0
CR0
0
0
0