LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 122

• Manufacturer Part Number: LAN9115-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1010

In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can
be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high
between bursts for the period specified.
Revision 1.5 (07-11-08)
6.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
A[7:5]
A[4:1]
Data Bus
ah
Note: The “Data Bus” width is 16 bits
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 LAN9115 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
122
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
165
13
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9115
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns