LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 38

• Manufacturer Part Number: LAN9115-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1010

Revision 1.5 (07-11-08)
3.9.2.2
3.9.2.3
3.9.2.4
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECS
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 3.8, "Required EECLK
each EEPROM operation.
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to
"E2P_DATA – EEPROM Data Register," on page 97
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to
OPERATION
ERASE
WRITE
EWDS
EWEN
READ
WRAL
ERAL
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 95
Section 6.9, "EEPROM Timing," on page 128
1
0
0
Figure 3.10 EEPROM WRAL Cycle
Table 3.8 Required EECLK Cycles
0
Cycles", shown below, shows the number of EECLK cycles required for
1
DATASHEET
38
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
REQUIRED EECLK CYCLES
D7
for detailed EEPROM timing specifications.
for a detailed description of these registers.
D0
10
10
10
10
18
18
18
t
CSL
and
Section 5.3.24,
SMSC LAN9115
Datasheet