LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 307

IC ETHER SW 2PRT 16BIT 128-VTQFP

LAN9311-NU

Manufacturer Part Number
LAN9311-NU
Description
IC ETHER SW 2PRT 16BIT 128-VTQFP
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheets

Specifications of LAN9311-NU

Controller Type
Ethernet Switch Controller
Interface
Serial EEPROM
Voltage - Supply
3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1076 - EVALUATION BOARD LAN9311-NU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1075

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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.4.2.12
BITS
15:8
7
6
5
4
3
2
1
0
RESERVED
INT7_MASK
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT6_MASK
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT3_MASK
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT2_MASK
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
RESERVED
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the
Index (decimal): 30
Port x PHY Interrupt Source Flags Register
DESCRIPTION
DATASHEET
307
Size:
16 bits
(PHY_INTERRUPT_SOURCE_x).
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
-
-

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