COM20020I3V-DZD SMSC, COM20020I3V-DZD Datasheet - Page 36

• Manufacturer Part Number: COM20020I3V-DZD
• Description: IC CTRLR LAN UNIV 2KX8 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20020I3V-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1002-5

Revision 12-05-06
3,2,1
BIT
7
6
5
4
0
Pulse1 Mode
Four NACKS
Reserved
Receive All
Clock Prescaler Bits
3,2,1
Slow Arbitration
Select
BIT NAME
P1MODE
FOUR
NACKS
RCVALL
CKP3,2,1
SLOWARB
SYMBOL
Table 6.10 -
DATASHEET
This bit determines the type of PULSE1 output driver used in
Backplane Mode. When high, a push/pull output is used. When
low, an open drain output is used. The default is open drain.
This bit, when set, will cause the EXNACK bit in the Diagnostic
Status Register to set after four NACKs to Free Buffer Enquiry are
detected by the COM20020ID. This bit, when reset, will set the
EXNACK bit after 128 NACKs to Free Buffer Enquiry. The default
is 128.
Do not set.
This bit, when set, allows the COM20020ID to receive all valid
data packets on the network, regardless of their destination ID.
This mode can be used to implement a network monitor with the
transmitter on- or off-line. Note that ACKs are only sent for
packets received with a destination ID equal to the COM20020ID's
programmed node ID. This feature can be used to put the
COM20020ID in a 'listen-only' mode, where the transmitter is
disabled and the COM20020ID is not passing tokens. Defaults
low.
These bits are used to determine the data rate of the
COM20020ID. The following table is for a 20 MHz crystal: (Clock
Multiplier is bypassed)
CKP3
0
0
0
0
1
NOTE: The lowest data rate achievable by the COM20020ID is
156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multiplier output
clock speed greater than 20 MHz, CKP3, CKP2 and CKP1 must
all be zero.
This bit, when set, will divide the arbitration clock by 2. Memory
cycle times will increase when slow arbitration is selected.
NOTE: For clock multiplier output clock speeds greater than 40
MHz, SLOWARB must be set. Defaults to low.
Page 36
Setup 1 Register
CKP2
0
0
1
1
0
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
CKP1
0
1
0
1
0
DESCRIPTION
DIVISOR
8
16
32
64
128
SPEED
2.5Mbs
1.25Mbs
625Kbs
312.5Kbs
156.25Kbs
SMSC COM20020I Rev D
Datasheet