COM20020I3V-DZD SMSC, COM20020I3V-DZD Datasheet - Page 53

• Manufacturer Part Number: COM20020I3V-DZD
• Description: IC CTRLR LAN UNIV 2KX8 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20020I3V-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1002-5

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Chapter 8
SMSC COM20020I Rev D
AD0-AD2,
D3-D7
nCS
ALE
DIR
nDS
*
Note 1:
Note 2:
T
T
T
T
t10
t11
t12
t13
t14
ARB
ARB
ARB
opr
Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
t1
t2
t3
t4
t5
t6
t7
t8
t9
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Timing Diagrams
nCS Hold from ALE Low
nDS High to Data High Impedance
Cycle Time (nDS Low to Next Time Low)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5T
the leading edge of the next nDS.
Address Hold from ALE Low
nCS Setup to ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
Address Setup to ALE Low
opr
if SLOW ARB = 1
t11
t1
opr
VALID
t3
if SLOW ARB = 0
MUST BE: RBUSTMG bit = 0
DATASHEET
Parameter
t2,
t4
t5
t9
Page 53
t6
ARB
from the trailing edge of nDS to
VALID DATA
t12
t13
4T
min
10
10
20
20
60
20
20
10
10
10
15
ARB
0
t8
*
max
40
20
t7
t10
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note 2
t14
Revision 12-05-06