FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 127

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

CR0C
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 0CH. The
default
CR0D
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 0DH.
This register is read only. This is the Device ID. The
default value of this register after power up is 03H.
value
BIT NO.
3, 4, 5
0
1
2
6
7
UART 2 Duplex This bit is used to define the FULL/HALF
UART 2 MODE UART 2 Mode
UART 1 Speed This bit enables the high speed mode of UART
UART 2 XMIT
UART 2 RCV
UART Speed
BIT NAME
of
Polarity
Polarity
Table 56 - CR0C
1 = RX input inverted.
0 = RX input non - inverted (default).
1 = TX output inverted.
0 = TX output non - inverted (default).
DUPLEX operation of UART 2.
1 = Half duplex
0 = Full duplex (default)
5 4 3
0 0 0Standard (default)
0 0 1IrDA (HPSIR)
0 1 0Amplitude Shift Keyed IR @ 500Khz
0 1 1Reserved
1 x xReserved
1 = High speed enabled
0 = Standard (default)
1 = High speed enabled
0 = Standard (default)
this
This bit enables the high speed mode of UART
127
register after power up is 00H. This register controls the
operating mode of the UART. This register is reset to the
default state by a POR or a hardware reset.
CR0E
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 0EH.
This register is read only. The default value of this
register after power up is 02H. This is used to identify the
chip revision level.
DESCRIPTION