FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 92

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

2.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Chip may modify nWRITE, PDIR and nPDATA in
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration
register, the standard and bi-directional modes are also
available. If no EPP Read, Write or Address cycle is
currently executing, then the PDx bus is in the standard
or bi-directional mode, and all output signals (STROBE,
AUTOFD, INIT) are as set by the SPP Control Port and
direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the
EPP timing. For this reason, a watchdog timer is required
If the EPP bus is ready (nWAIT is inactive high)
then the chip must wait for it to go active low before
changing the state of WRITE or before nDATASTB
goes active. The read can complete once nWAIT is
determined inactive.
The host selects an EPP register and drives nIOR
active.
The chip drives IOCHRDY inactive (low).
If WAIT is not asserted, the chip must wait until
WAIT is asserted.
The chip tri-states the PData bus and deasserts
nWRITE.
Chip asserts nDATASTB or nADDRSTRB indicating
that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
Peripheral drives PData bus valid.
Peripheral
PData is valid and the chip may begin the
termination phase of the cycle.
a)
b)
Peripheral tri-states the PData bus and asserts
nWAIT, indicating to the host that the PData bus is
tri-stated.
preparation for the next cycle.
The chip latches the data from the PData bus
for the SData bus, deasserts nDATASTB or
nADDRSTRB, this marks the beginning of the
termination phase.
The chip drives the valid data onto the SData
bus and asserts (releases) IOCHRDY allowing
the host to complete the read cycle.
deasserts
nWAIT,
indicating that
92
to prevent system lockup. The timer indicates if more
than 10usec have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the cycle nIOR
or nIOW deasserted). If a time-out occurs, the current
EPP cycle is aborted and the time-out condition is
indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software must
ensure that the control register bits D0, D1 and D3 are set
to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write
or a logic "1" for and EPP read.
EPP 1.7 Write
The timing for a write operation (address or data) is
shown in timing diagram EPP 1.7 Write Data or Address
cycle. IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be used to
extend the cycle time.
when nWAIT is inactive high.
Write Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
The host sets PDIR bit in the control register to a
logic "0". This asserts nWRITE.
The host selects an EPP register, places data on the
SData bus and drives nIOW active.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating
that PData bus contains valid information, and the
WRITE signal is valid.
If nWAIT is asserted, IOCHRDY is deasserted
until the peripheral deasserts nWAIT or a time-out
occurs.
When the host deasserts nI0W the chip deasserts
nDATASTB or nADDRSTRB and latches the data
from the SData bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in
preparation of the next cycle.
The write cycle can complete