FDC37C669-MT SMSC, FDC37C669-MT Datasheet - Page 99

• Manufacturer Part Number: FDC37C669-MT
• Description: IC CTRLR SUPER I/O FLPPY 100TQFP
• Manufacturer: SMSC

Specifications of FDC37C669-MT

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1008

DATA and ecpAFifo PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of '00H' from the
base address. The data register is cleared at initialization
by RESET.
Register latches the contents of the data bus on the rising
edge of the nIOW input.
are buffered (non inverting) and output onto the PD0 -
PD7 ports. During a READ operation, PD0 - PD7 ports
are read and output to the host CPU.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in the FIFO
and tagged as an ECP Address/RLE. The hardware at
the ECP port transmits this byte to the peripheral
automatically.
defined for the forward direction (direction is 0). Refer to
the ECP Parallel Port Forward Timing Diagram, located in
the Timing Diagrams section of this data sheet.
DEVICE STATUS REGISTER (dsr)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the
base address. Bits 0 - 2 are not implemented as register
bits, during a read of the Printer Status Register these
bits are a low level.
defined as follows:
BIT 3 nFault
The level on the nFault input is read by the CPU as bit 3
of the Device Status Register.
BIT 4 Select
The level on the Select input is read by the CPU as bit 4
of the Device Status Register.
During a WRITE operation, the Data
The operation of this register is only
The bits of the Status Port are
The contents of this register
99
BIT 5 PError
The level on the PError input is read by the CPU as bit 5
of the Device Status Register. Printer Status Register.
BIT 6 nAck
The level on the nAck input is read by the CPU as bit 6
of the Device Status Register.
BIT 7 nBusy
The complement of the level on the BUSY input is read
by the CPU as bit 7 of the Device Status Register.
DEVICE CONTROL REGISTER (dcr)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of '02H' from
the base address. The Control Register is initialized to
zero by the RESET input, bits 0 to 5 only being affected;
bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the nAUTOFD output.
each line is printed. A logic 0 means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
BIT 3 SELECTIN
This bit is inverted and output onto the nSLCTIN output.
A logic 1 on this bit selects the printer; a logic 0 means
the printer is not selected.
BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level
may be used to enable interrupt
A logic 1 causes the printer to generate a line feed after