DP8390DV National Semiconductor, DP8390DV Datasheet - Page 35

• Manufacturer Part Number: DP8390DV
• Description: IC CTRLR NETWORK IN (NIC)68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8390DV

• Controller Type: Network Interface Controller (NIC)
• Voltage - Supply: 5V
• Current - Supply: 40mA
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP8390DV

13 0 Bus Arbitration and Timing
When in 32-bit mode four additional BSCK cycles are re-
quired per burst The first bus cycle (T1 – T4 ) of each burst
is used to output the upper 16-bit addresses This 16-bit
address is programmed in RSAR0 and RSAR1 and points to
a 64k page of system memory All transmitted or received
packets are constrained to reside within this 64k page
FIFO BURST CONTROL
All Local DMA transfers are burst transfers once the DMA
requests the bus and the bus is acknowledged the DMA will
where N
INTERLEAVED LOCAL OPERATION
If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted the Remote DMA
transfer will be interrupted for higher priority Local DMA
Note that if the FIFO requires service while a remote DMA is
in progress BREQ is not dropped and the Local DMA burst
is appended to the Remote Transfer When switching from
a local transfer to a remote transfer however BREQ is
dropped and raised again This allows the CPU or other
devices to fairly contend for the bus
REMOTE DMA-BIDIRECTIONAL PORT CONTROL
The Remote DMA transfers data between the local buffer
memory and a bidirectional port (memory to I O transfer)
e
1 2 4 or 6 Words or N
e
2 4 8 or 12 Bytes when in byte mode
Bus Handshake Signals for Remote DMA Transfers
(Continued)
35
transfer an exact burst of bytes programmed in the Data
Configuration Register (DCR) then relinquish the bus If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded If BACK is
removed during the transfer the burst transfer will be abort-
ed (DROPPING BACK DURING A DMA CYCLE IS NOT
RECOMMENDED )
transfers When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers This is illustrated below
This transfer is arbited on a byte by byte basis versus the
burst transfer used for Local DMA transfers This bidirec-
tional port is also read written by the host All transfers
through this port are asynchronous At any one time trans-
fers are limited to one direction either from the port to local
buffer memory (Remote Write) or from local buffer memory
to the port (Remote Read)
TL F 8582 – 71
TL F 8582– 69
TL F 8582 – 70