PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 138

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

The HDLC controller will request another data block by an XPR interrupt if there are no more
than 32 bytes in XFIFO and the frame close command bit (Transmit Message End XME) has
not been set. To this the microcontroller responds by writing another pool of data and re-
issuing a transmit command for that pool. When XME is set, all remaining bytes in XFIFO are
transmitted, the CRC field and the closing flag of the HDLC frame are appended and the
controller generates a new XPR interrupt.
The microcontroller does not necessarily have to transfer a frame in blocks of 32 bytes. As a
matter of fact, the sub-blocks issued by the microcontroller and separated by a transmit
command, can be between 0 and 32 bytes long.
If the XFIFO runs out of data and the XME command bit has not been set, the frame will be
terminated with an abort sequence (seven 1’s) followed by inter-frame time fill, and the
microcontroller will be advised by a Transmit Data Underrun (XDU) interrupt. An HDLC frame
may also be aborted by setting the Transmitter Reset (XRES) command bit.
3.5
After a hardware reset (pin RST), layer 1 will have reached the following state:
– F3 standby
according to CCITT I.430.
F3 standby state means that the internal oscillator, the DCL clock and FSC1 are active.
During the reset pulse pin SDS1 is "low", all other pins are in high impedance state. The S/T
interface awake detector is active after reset. The F3 power down state, where the internal
oscillator itself is disabled, can be reached by setting the CFS bit (SQXR register) to logical "1".
A subset of ISAC-S TE registers with defined reset values is listed in table 14.
Table 14
State of ISAC
Register (address (hex))
ISTA
MASK
EXIR
STAR
CMDR
Semiconductor Group
Reset
(20)
(20)
(24)
(21)
(21)
®
-S TE Registers after Hardware Reset
Value after
Reset (hex)
00
00
00
48 (4A)
00
138
Meaning
No interrupts
All interrupts enabled
No interrupts
– XFIFO is ready to be written to
– RFIFO is ready to receive at least 16 octets of
No command
a new message
Operational Description