PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 153

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

The internal timer procedure will be started in auto-mode:
VALUE Determines the Time Period T1:
Semiconductor Group
The timer procedure will be stopped when
Note: The maximum value of CNT can be 6. If CNT is set to 7, the number of retries
* External Timer Mode (TMD = 0)
CNT together with VALUE determine the time period T2 after which a TIN interrupt
will be generated:
CNT 2.048 s + T1
with T1 = (VALUE + 1) 0.064 s,
in the normal case, and
T2 = 16348 CNT DCL + T1
with T1 = 512 (VALUE + 1) DCL
when TLP = 1 (test loop activated, SPCR register).
DCL denotes the period of the DCL clock.
The timer can be started by setting the STI bit in CMDR and will be stopped when a
TIN interrupt is generated or the TIMR register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every
T1 = (VALUE + 1) 0.064 s (SPCR:TLP = 0, normal mode)
T1 = 512 (VALUE + 1) DCL (SPCR:TLP = 1, test mode).
– after start of an I-frame transmission
or
– after an "RNR" S frame has been received.
After the last retry, a timer interrupt (TIN bit in ISTA) is generated.
– a TIN interrupt is generated. The time between the start of an I-frame
– or the TIMR is written
– or a positive or negative acknowledgement has been received.
transmission or reception of an "RNR" S frame and the generation of a TIN
interrupt is equal to: (CNT+1) T1.
is unlimited.
expiration of T1.
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Register Description