PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet

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PIC18F4550-I/PT

Manufacturer Part Number
PIC18F4550-I/PT
Description
44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/PT

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18F2455/2550/4455/4550
Data Sheet
28/40/44-Pin, High-Performance,
Enhanced Flash, USB Microcontrollers
with nanoWatt Technology
Preliminary
© 2006 Microchip Technology Inc.
DS39632C

Related parts for PIC18F4550-I/PT

PIC18F4550-I/PT Summary of contents

Page 1

... PIC18F2455/2550/4455/4550 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers © 2006 Microchip Technology Inc. Data Sheet with nanoWatt Technology Preliminary DS39632C ...

Page 2

... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ © 2006 Microchip Technology Inc. ...

Page 3

... PIC18F2550 32K 16384 2048 PIC18F4455 24K 12288 2048 PIC18F4550 32K 16384 2048 © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Peripheral Highlights: • High-Current Sink/Source: 25 mA/25 mA • Three External Interrupts • Four Timer modules (Timer0 to Timer3) • Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max ...

Page 4

... REF USB Preliminary RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 (1) RB3/AN9/CCP2 /VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA RC7/RX/DT/SDO RC6/TX/CK RC5/D+/VP RC4/D-/VM RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0/CSSPP (1) RB3/AN9/CCP2 /VPO RB2/AN8/INT2/VMO RB1/AN10/INT1/SCK/SCL RB0/AN12/INT0/FLT0/SDI/SDA RD7/SPP7/P1D RD6/SPP6/P1C RD5/SPP5/P1B RD4/SPP4 RC7/RX/DT/SDO RC6/TX/CK RC5/D+/VP RC4/D-/VM RD3/SPP3 RD2/SPP2 © 2006 Microchip Technology Inc. ...

Page 5

... Microchip Technology Inc. PIC18F2455/2550/4455/4550 33 NC/ICRST 1 32 RC0/T1OSO/T13CKI 2 31 OSC2/CLKO/RA6 3 OSC1/CLKI PIC18F4455 PIC18F4550 27 RE2/AN7/OESPP 7 26 RE1/AN6/CK2SPP 8 25 RE0/AN5/CK1SPP 9 24 RA5/AN4/SS/HLVDIN/C2OUT 10 23 RA4/T0CKI/C1OUT/RCV 11 1 RD4/SPP4 2 RD5/SPP5/P1B 3 RD6/SPP6/P1C 4 PIC18F4455 RD7/SPP7/P1D PIC18F4550 Preliminary (2) PP (2) /ICV 33 OSC2/CLKO/RA6 32 OSC1/CLKI RE2/AN7/OESPP 26 RE1/AN6/CK2SPP 25 RE0/AN5/CK1SPP 24 RA5/AN4/SS/HLVDIN/C2OUT 23 RA4/T0CKI/C1OUT/RCV DS39632C-page 3 ...

Page 6

... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 411 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 411 Index .................................................................................................................................................................................................. 413 The Microchip Web Site ..................................................................................................................................................................... 425 Customer Change Notification Service .............................................................................................................................................. 425 Customer Support .............................................................................................................................................................................. 425 Reader Response .............................................................................................................................................................................. 426 PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 427 DS39632C-page 4 Preliminary © 2006 Microchip Technology Inc. ...

Page 7

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Preliminary DS39632C-page 5 ...

Page 8

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 6 Preliminary © 2006 Microchip Technology Inc. ...

Page 9

... PIC18LF2455 • PIC18F2550 • PIC18LF2550 • PIC18F4455 • PIC18LF4455 • PIC18F4550 • PIC18LF4550 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high endurance, Enhanced Flash program mem- ory ...

Page 10

... Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2550), accommodate an operating V Low-voltage parts, designated by “LF” (such as PIC18LF2550), function over an extended V of 2.0V to 5.5V. Preliminary © 2006 Microchip Technology Inc. (24 Kbytes for 32 Kbytes for range of 4.2V to 5.5V. DD ...

Page 11

... WDT WDT Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set Instruction Set enabled enabled 28-pin PDIP 28-pin PDIP 28-pin SOIC 28-pin SOIC Preliminary PIC18F4455 PIC18F4550 DC – 48 MHz DC – 48 MHz 24576 32768 12288 16384 2048 2048 256 256 20 20 Ports Ports ...

Page 12

... USB 10-Bit Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT OSC2/CLKO/RA6 PORTB RB0/AN12/INT0/FLT0/SDI/SDA RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO (3) RB3/AN9/CCP2 /VPO RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (3) RC1/T1OSI/CCP2 /UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT/SDO PORTE (1) MCLR/V /RE3 PP © 2006 Microchip Technology Inc. ...

Page 13

... These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features (Designated Packages Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Bus<8> Data Latch ...

Page 14

... Crystal Oscillator mode. O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2006 Microchip Technology Inc. ...

Page 15

... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...

Page 16

... Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description 2 C mode. © 2006 Microchip Technology Inc. ...

Page 17

... ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...

Page 18

... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2006 Microchip Technology Inc. ...

Page 19

... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer ...

Page 20

... Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description 2 C mode. © 2006 Microchip Technology Inc. ...

Page 21

... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer ...

Page 22

... TTL Streaming Parallel Port data. O — Enhanced CCP1 PWM output, channel C. 5 I/O ST Digital I/O. I/O TTL Streaming Parallel Port data. O — Enhanced CCP1 PWM output, channel D. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2006 Microchip Technology Inc. ...

Page 23

... Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Pin Buffer ...

Page 24

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 22 Preliminary © 2006 Microchip Technology Inc. ...

Page 25

... PIC18F2455/2550/4455/4550 devices can be operated in twelve distinct oscillator modes. In contrast with pre- vious PIC18 enhanced microcontrollers, four of these modes involve the use of two oscillator types at once. Users can program the FOSC3:FOSC0 Configuration bits to select one of these modes: © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 1. XT Crystal/Resonator 2. ...

Page 26

... OSCTUNE<7> Preliminary USB Clock Source FSEN 1 USB Peripheral 0 4 CPU Primary Clock IDLEN Peripherals Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2006 Microchip Technology Inc. ...

Page 27

... DD See the notes following Table 2-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 2-2: Osc Type XT HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...

Page 28

... MHz which drives the PLL directly. FIGURE 2-6: PLL BLOCK DIAGRAM (HS MODE) HS/EC/ECIO/XT Oscillator Enable PLL Enable (from CONFIG1H Register) OSC2 Oscillator F IN and OSC1 F OUT Prescaler 24 Preliminary © 2006 Microchip Technology Inc. Phase Comparator Loop Filter VCO SYSCLK ...

Page 29

... OSC1/CLKI; the OSC2/ CLKO pin functions as a digital I/O (RA6). Of these four modes, only INTIO mode frees up an additional pin (OSC2/CLKO/RA6) for port I/O use. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 2.2.5.2 OSCTUNE Register The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’ ...

Page 30

... OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. Preliminary R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 31

... Oscillator Settings for USB When the PIC18F4550 is used for USB connectivity, it must have either a 6 MHz or 48 MHz clock for USB operation, depending on whether Low-Speed or Full-Speed mode is being used. This may require some forethought in selecting an oscillator frequency and programming the device. ...

Page 32

... MHz 16 MHz 8 MHz 5.33 MHz 4 MHz 48 MHz 32 MHz 24 MHz 16 MHz 12 MHz 6 MHz 4 MHz 3 MHz 48 MHz 32 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2.67 MHz 2 MHz 48 MHz 32 MHz 24 MHz 16 MHz 4 MHz 2 MHz 1.33 MHz 1 MHz 48 MHz 32 MHz 24 MHz 16 MHz © 2006 Microchip Technology Inc. ...

Page 33

... The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The Internal IRCF2:IRCF0, select the frequency output of the internal oscillator block to drive the device clock ...

Page 34

... Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 35

... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 command over the USB. Once the module has sus- pended operation and shifted to a low-power state, the microcontroller may be safely put into Sleep mode ...

Page 36

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 34 Preliminary © 2006 Microchip Technology Inc. ...

Page 37

... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...

Page 38

... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary © 2006 Microchip Technology Inc. has started. In such ...

Page 39

... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 n-1 ...

Page 40

... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) (1) T PLL 1 2 n-1 n (2) Clock Transition OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. . OSC Preliminary © 2006 Microchip Technology Inc. ...

Page 41

... Wake Event Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3.4 Idle Modes in the The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...

Page 42

... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2006 Microchip Technology Inc. ...

Page 43

... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON< ...

Page 44

... XTPLL, HSPLL T OST CSD ( (3) INTOSC T IOBST . PLL (parameter 39, Table 28-12), the INTOSC stabilization period. IOBST Preliminary Clock Ready Status Bit (OSCCON) OSTS IOFS ( OSTS rc (2) IOFS ( OSTS rc (2) IOFS ( OSTS rc (5) IOFS is the PLL lock time-out rc © 2006 Microchip Technology Inc. ...

Page 45

... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. ...

Page 46

... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39632C-page 44 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 47

... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 4- ...

Page 48

... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Preliminary © 2006 Microchip Technology Inc. ...

Page 49

... INTHS, INTXT 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...

Page 50

... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39632C-page 48 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2006 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...

Page 51

... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the Power-up Timer. PLL © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 , V RISE > PWRT T OST T PWRT T ...

Page 52

... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Preliminary STKPTR Register POR BOR STKFUL STKUNF © 2006 Microchip Technology Inc. ...

Page 53

... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, ...

Page 54

... Microchip Technology Inc. ...

Page 55

... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, ...

Page 56

... Microchip Technology Inc. ...

Page 57

... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 MCLR Resets, Power-on Reset, ...

Page 58

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 56 Preliminary © 2006 Microchip Technology Inc. ...

Page 59

... The PIC18F2455 and PIC18F4455 each have 24 Kbytes of Flash memory and can store up to 12,288 single-word PIC18F4550 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...

Page 60

... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack<20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2006 Microchip Technology Inc. ...

Page 61

... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...

Page 62

... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary © 2006 Microchip Technology Inc. ...

Page 63

... Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...

Page 64

... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2006 Microchip Technology Inc. ...

Page 65

... Additional information on USB RAM and buffer operation is provided in Section 17.0 “Universal Serial Bus (USB)”. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 5.3.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...

Page 66

... RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2006 Microchip Technology Inc. ...

Page 67

... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Data Memory 000h ...

Page 68

... UEIE LATB F6Ah UEIR LATA F69h UIE (2) — F68h UIR (2) — F67h UFRMH (2) — F66h UFRML (2) (3) — F65h SPPCON (3) PORTE F64h SPPEPS (3) (3) PORTD F63h SPPCFG (3) PORTC F62h SPPDATA (2) PORTB F61h — (2) PORTA F60h — © 2006 Microchip Technology Inc. ...

Page 69

... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> Slave mode only. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 4 Bit 3 Bit 2 — Top-of-Stack Upper Byte (TOS<20:16>) — ...

Page 70

... TMR3CS TMR3ON 53, 137 0000 0000 53, 241 0000 0000 53, 241 0000 0000 53, 250 0000 0000 53, 247 0000 0000 TRMT TX9D 53, 238 0000 0010 OERR RX9D 53, 239 0000 000x © 2006 Microchip Technology Inc. ...

Page 71

... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> Slave mode only. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 4 Bit 3 Bit 2 — FREE ...

Page 72

... URSTIE 55, 180 -000 0000 UERRIF URSTIF 55, 178 -000 0000 FRM9 FRM8 55, 170 ---- -xxx FRM1 FRM0 55, 170 xxxx xxxx SPPOWN SPPEN 55, 187 ---- --00 ADDR1 ADDR0 55, 191 00-0 0000 WS1 WS0 55, 188 0000 0000 DATA1 DATA0 55, 192 0000 0000 © 2006 Microchip Technology Inc. ...

Page 73

... For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 It is recommended that only BCF, BSF, SWAPF, MOVFF ...

Page 74

... Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary © 2006 Microchip Technology Inc. ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...

Page 75

... ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...

Page 76

... Indirect Addressing. Similarly, operations by Indirect Addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. Preliminary © 2006 Microchip Technology Inc. ...

Page 77

... Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When using the extended instruction set, this addressing mode requires the following: • ...

Page 78

... F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory Preliminary © 2006 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...

Page 79

... F00h BSR. F60h FFFh © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...

Page 80

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 78 Preliminary © 2006 Microchip Technology Inc. ...

Page 81

... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 82

... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Preliminary Table Latch (8-bit) TABLAT © 2006 Microchip Technology Inc. ...

Page 83

... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-x R/W-0 ...

Page 84

... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE ERASE TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 © 2006 Microchip Technology Inc. ...

Page 85

... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

Page 86

... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2006 Microchip Technology Inc. ...

Page 87

... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...

Page 88

... TBLWT holding register. ; loop until buffers are full Preliminary © 2006 Microchip Technology Inc. ...

Page 89

... USBIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...

Page 90

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 88 Preliminary © 2006 Microchip Technology Inc. ...

Page 91

... EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory ...

Page 92

... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39632C-page 90 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 93

... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times except when updating the EEPROM ...

Page 94

... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts Preliminary information (e.g., program © 2006 Microchip Technology Inc. ...

Page 95

... EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE ...

Page 96

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 94 Preliminary © 2006 Microchip Technology Inc. ...

Page 97

... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...

Page 98

... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2006 Microchip Technology Inc. ...

Page 99

... INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the ...

Page 100

... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2006 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL GIE/GIEH ...

Page 101

... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Note: Interrupt flag bits are set when an interrupt ...

Page 102

... This feature allows for software polling. DS39632C-page 100 R/W-1 U-0 R/W-1 — INTEDG2 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 103

... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 ...

Page 104

... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2006 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...

Page 105

... A TMR1 or TMR3 register capture occurred (must be cleared in software TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...

Page 106

... Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632C-page 104 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 107

... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...

Page 108

... Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear. DS39632C-page 106 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 109

... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 110

... The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. DS39632C-page 108 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 111

... USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 9.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...

Page 112

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 110 Preliminary © 2006 Microchip Technology Inc. ...

Page 113

... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. ...

Page 114

... LATA<6> data output. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as ‘0’. IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO modes; otherwise, reads as ‘0’. Preliminary Description /4); available in EC, ECPLL and OSC © 2006 Microchip Technology Inc. ...

Page 115

... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 ...

Page 116

... MOVLW 0Eh ; Set RB<4:0> as MOVWF ADCON1 ; digital I/O pins ; (required if config bit ; PBADEN is set) MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs Preliminary © 2006 Microchip Technology Inc. ...

Page 117

... Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1. 3: All other pin functions are disabled when ICSP™ or ICD operation is enabled. 4: 40/44-pin devices only. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type DIG LATB<0> data output; not affected by analog input. ...

Page 118

... PKTDIS USBEN RESUME SUSPND Preliminary Description (3) (3) (3) Reset Bit 2 Bit 1 Bit 0 Values on page RB2 RB1 RB0 54 LATB1 LATB0 54 TRISB1 TRISB0 54 INT0IF RBIF 51 — RBIP 51 — INT2IF INT1IF 51 PCFG1 PCFG0 52 — SPPOWN SPPEN 55 WS2 WS1 WS0 55 — 55 © 2006 Microchip Technology Inc. ...

Page 119

... When the external transceiver is enabled, RC2 also serves as the output enable control to the transceiver. Additional information on configuring USB options is provided in Section 17.2.2.2 “External Transceiver”. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 When enabling peripheral functions on PORTC pins other than RC4 and RC5, care should be taken in defin- ing the TRIS bits ...

Page 120

... Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as output. OUT DIG Synchronous serial clock output (EUSART module); takes priority over port data Synchronous serial clock input (EUSART module). Preliminary Description © 2006 Microchip Technology Inc. ...

Page 121

... UCON — PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC. Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATC< ...

Page 122

... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2006 Microchip Technology Inc. ...

Page 123

... SPP7 1 1 P1D 0 Legend: OUT = Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: May be configured for tri-state during Enhanced PWM shutdown events. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 I/O I/O Type OUT DIG LATD<0> data output PORTD< ...

Page 124

... TRISD4 TRISD3 TRISD2 (1,2) — — RE3 RE2 DC1B1 DC1B0 CCP1M3 CCP1M2 — — — — Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 54 LATD1 LATD0 54 TRISD1 TRISD0 54 (3) (3) (3) RE1 RE0 54 CCP1M1 CCP1M0 53 SPPOWN SPPEN 55 © 2006 Microchip Technology Inc. ...

Page 125

... RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: Unimplemented in 28-pin devices; read as ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Config- uration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...

Page 126

... PCFG3 PCFG2 C2INV C1INV CIS CM2 — — — CSEN CLK1EN WS3 WS2 Preliminary Description Reset Bit 1 Bit 0 Values on page (3) (3) (3) RE1 RE0 54 LATE1 LATE0 54 TRISE1 TRISE0 54 PCFG1 PCFG0 52 CM1 CM0 53 — SPPOWN SPPEN 55 WS1 WS0 55 © 2006 Microchip Technology Inc. ...

Page 127

... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...

Page 128

... Sync with Internal Clocks Delay Preliminary ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0L TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...

Page 129

... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 11.3.1 SWITCHING PRESCALER ...

Page 130

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 128 Preliminary © 2006 Microchip Technology Inc. ...

Page 131

... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...

Page 132

... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...

Page 133

... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...

Page 134

... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary a Special Event Trigger © 2006 Microchip Technology Inc. ...

Page 135

... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 ; Preload TMR1 register pair ; for 1 second overflow ...

Page 136

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 134 Preliminary © 2006 Microchip Technology Inc. ...

Page 137

... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...

Page 138

... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 51 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP © 2006 Microchip Technology Inc. ...

Page 139

... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...

Page 140

... Clear TMR3 TMR3L 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...

Page 141

... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...

Page 142

... PIC18F2455/2550/4455/4550 NOTES: DS39632C-page 140 Preliminary © 2006 Microchip Technology Inc. ...

Page 143

... Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCPxIF bit is set) 11xx = PWM mode Note 1: These bits are not implemented on 28-pin devices and are read as ‘0’. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. ...

Page 144

... Changing the pin assignment of CCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropri- ate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction Preliminary © 2006 Microchip Technology Inc. ...

Page 145

... CCP1CON<3:0> Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...

Page 146

... Set CCP1IF Output Compare Match Logic 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Preliminary Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2006 Microchip Technology Inc. ...

Page 147

... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Bit 5 Bit 4 Bit 3 ...

Page 148

... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Preliminary • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2006 Microchip Technology Inc. ...

Page 149

... The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 EQUATION 15-3: PWM Resolution (max) Note: ...

Page 150

... PDC5 PDC4 PDC3 PDC2 Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 51 PD POR BOR 52 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP 54 TRISB1 TRISB0 54 TRISC1 TRISC0 CCP1M1 CCP1M0 CCP2M1 CCP2M0 53 (2) (2) PSSBD0 53 (2) (2) (2) PDC1 PDC0 53 © 2006 Microchip Technology Inc. ...

Page 151

... PWM mode: P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, ...

Page 152

... PWM. and Timer RC2 RD5 All PIC18F4455/4550 devices: CCP1 RD5/SPP5 P1A P1B P1A P1B Preliminary and Section 15.3 “Compare for PWM Operation” or RD6 RD7 RD6/SPP6 RD7/SPP7 RD6/SPP6 RD7/SPP7 P1C P1D © 2006 Microchip Technology Inc. ...

Page 153

... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...

Page 154

... The general relationship of the outputs in all configurations is summarized in Figure 16-2 and Figure 16-3. 9.77 kHz 39.06 kHz FFh FFh Preliminary OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2006 Microchip Technology Inc. ...

Page 155

... Prescale Value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 0 Duty Cycle Period (1) Delay Delay ...

Page 156

... Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary Period (1) ( FET Driver FET Driver © 2006 Microchip Technology Inc. ...

Page 157

... P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTD<7> data latches. The TRISC<2>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...

Page 158

... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD © 2006 Microchip Technology Inc. ...

Page 159

... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...

Page 160

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ( cycles, between the scheduled and actual time for a PWM OSC OSC Preliminary modules, a low level on the the PSSAC1:PSSAC0 and R/W-0 R/W-0 (1) (1) (1) PDC1 PDC0 bit Bit is unknown ) © 2006 Microchip Technology Inc. ...

Page 161

... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...

Page 162

... PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle Preliminary © 2006 Microchip Technology Inc. ECCPASE Cleared by Firmware ...

Page 163

... Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...

Page 164

... POR BOR 52 TMR2IP TMR1IP 54 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR3IP CCP2IP 54 TMR3IF CCP2IF 54 TMR3IE CCP2IE 54 TRISB1 TRISB0 54 TRISC1 TRISC0 54 TRISD1 TRISD0 TMR1CS TMR1ON 52 52 T2CKPS1 T2CKPS0 TMR3CS TMR3ON CCP1M1 CCP1M0 53 (2) (2) PSSBD1 PSSBD0 53 (2) (2) (2) PDC1 PDC0 53 © 2006 Microchip Technology Inc. ...

Page 165

... Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1). 2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used not enable the internal regulator when using an external 3.3V supply. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The SIE can be interfaced directly to the USB, utilizing the internal transceiver can be connected through an external transceiver ...

Page 166

... R/C-0 R/W-0 R/W-0 PKTDIS USBEN RESUME U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 U-0 SUSPND — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 167

... Bus Speed (full speed versus low speed) • On-Chip Pull-up Resistor Enable • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. ...

Page 168

... SIE that can’t be captured with the RCV signal. The combinations of states of these signals and their interpretation are listed in Table 17-1 and Table 17-2. Preliminary R/W-0 R/W-0 PPB1 PPB0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 169

... D+ D- Note: The above setting shows a typical connection for a full-speed configuration using an on-chip regulator and an external pull-up resistor. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.2.2.5 Ping-Pong Buffer Configuration The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong Buffering” ...

Page 170

... FIFO for USTAT Data Bus R-x R-x R-x ENDP1 ENDP0 DIR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary is full, the SIE will Clearing TRNIF Advances FIFO R-x U-0 (1) PPBI — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 171

... EPSTALL: Endpoint Stall Enable bit 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 transactions. For Endpoint 0, this bit should always be cleared since the Endpoint 0 as the default control endpoint. ...

Page 172

... RAM) used for Banks Bank15 Preliminary IMPLEMENTATION OF USB RAM IN DATA MEMORY SPACE 000h User Data 3FFh 400h Buffer Descriptors, USB Data or User Data 4FFh 500h USB Data or User Data 7FFh 800h Unused F00h F60h SFRs FFFh © 2006 Microchip Technology Inc. ...

Page 173

... Buffer descriptors not only define the size of an end- point buffer, but also determine its configuration and control. Most of the configuration is done with the BD Status register, BDnSTAT. Each BD has its own unique and correspondingly numbered BDnSTAT register. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 17-6: Address 400h ...

Page 174

... DTSEN Device Response after Receiving Packet DTS Handshake UOWN TRNIF ACK ACK ACK ACK ACK NAK Preliminary “BD Byte Count” for more BDnSTAT and USTAT Status Updated Not Updated Updated Not Updated Updated Not Updated © 2006 Microchip Technology Inc. ...

Page 175

... OUT token. Together with BC<7:0>, the valid byte counts are 0-1023. Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN = 1. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-x R/W-x INCDIS DTSEN U = Unimplemented bit, read as ‘ ...

Page 176

... R/W-x R/W-x R/W-x PID2 PID1 PID0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary When developing USB R/W-x R/W-x BC9 BC8 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 177

... Maximum BDs: 32 (BD0 to BD31) 33 (BD0 to BD32) Note: Memory area not shown to scale. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. ...

Page 178

... Bit 2 Bit 1 Bit 0 (2) PID0 BC9 BC8 (3) BSTALL © 2006 Microchip Technology Inc. ...

Page 179

... The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Figure 17-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts ...

Page 180

... The flag bits can also be set in software which can aid in firmware debugging. R/W-0 R/W-0 R/W-0 (1) (2) (3) IDLEIF TRNIF ACTVIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Preliminary R-0 R/W-0 (4) UERRIF URSTIF bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 181

... LOOP DONE: C: UCONbits.SUSPND = 0; while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; } © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 hardware is synchronized may not have an effect on the value of ACTVIF. Additionally, if the USB module uses the clock from the 96 MHz PLL source, then after clearing the SUSPND bit, the USB module may not be immediately operational while waiting for the 96 MHz PLL to lock ...

Page 182

... The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. R/W-0 R/W-0 R/W-0 IDLEIE TRNIE ACTVIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 UERRIE URSTIE bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 183

... PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 Each error bit is set as soon as the error condition is detected. Thus, the interrupt will typically not correspond with the end of a token being processed. ...

Page 184

... R/W-0 R/W-0 R/W-0 BTOEE DFN8EE CRC16EE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CRC5EE PIDEE bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 185

... USB when no internal power is available. Figure 17-12 shows a simple Dual Power with Self-Power Dominance example, which automatically switches between Self-Power Only and USB Bus Power Only modes. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 FIGURE 17-12: V BUS ...

Page 186

... CRC5EF PIDEF 55 CRC5EE PIDEE 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 EPINEN EPSTALL 55 © 2006 Microchip Technology Inc. ...

Page 187

... Figure 17-9 shows an example of a transaction within a frame. FIGURE 17-13: USB LAYERS Interface Endpoint Endpoint © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 17.10.3 TRANSFERS There are four transfer types defined in the USB specification. • Isochronous: This type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured ...

Page 188

... USB device. In custom applications, a driver may need to be developed. Fortunately, drivers are available for most common host systems for the most common classes of devices. Thus, these drivers can be reused. Preliminary © 2006 Microchip Technology Inc. about the layer Framework”) they optionally support ...

Page 189

... Microcontroller directly controls the SPP bit 0 SPPEN: SPP Enable bit 1 = SPP is enabled 0 = SPP is disabled © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 In addition, the SPP can provide time multiplexed addressing information along with the data by using the second strobe output. Thus, the USB endpoint number can be written in conjunction with the data for that endpoint ...

Page 190

... The SPP data lines (SPP<7:0>) are equipped with internal pull-ups for applications that may leave the port in a high-impedance condition. The pull-ups are enabled using the control bit, RDPU (PORTE<7>). Preliminary R/W-0 R/W-0 WS1 WS0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 191

... TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES) USB Clock OESPP CSSPP CK1SPP CK2SPP Write Address SPP<7:0> 2 Wait States © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 DATA Write Data Read Data MOVWF SPPDATA MOVF SPPDATA, W Write Data 2 Wait States 2 Wait States ...

Page 192

... SPPEPS or SPPDATA registers do not overrun the wait time due to the wait state setting. Write USB endpoint number to SPP Write outbound USB data to SPP or read inbound USB data from SPP Byte 2 Byte 3 Byte n Preliminary © 2006 Microchip Technology Inc. ...

Page 193

... Endpoint Address 15 • • • • 0001 0000 = Endpoint Address 0 © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 3. Read the data from the SPPDATA register; the data from the previous read operation is returned. The SPP automatically starts the read cycle for the next read. ...

Page 194

... TXIE SSPIE CCP1IE RCIP TXIP SSPIP CCP1IP (1,2) — — RE3 RE2 Preliminary Reset Bit 1 Bit 0 Values on page SPPOWN SPPEN 55 WS1 WS0 55 ADDR1 ADDR0 55 DATA1 DATA0 55 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP 54 (3) (3) (3) RE1 RE0 54 © 2006 Microchip Technology Inc. ...

Page 195

... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 19.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of the SPI are supported ...

Page 196

... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 197

... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 R/W-0 R/W-0 R/W-0 CKP ...

Page 198

... Example 19-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. Preliminary © 2006 Microchip Technology Inc. ...

Page 199

... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2006 Microchip Technology Inc. PIC18F2455/2550/4455/4550 19.3.4 TYPICAL CONNECTION Figure 19-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...

Page 200

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 © 2006 Microchip Technology Inc. ...

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