PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 187

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PIC18F4550-I/PT

Manufacturer Part Number
PIC18F4550-I/PT
Description
44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/PT

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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17.10 Overview of USB
This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
section serves as a basic, high-level refresher of USB.
17.10.1
USB device functionality is structured into a layered
framework graphically shown in Figure 17-13. Each
level is associated with a functional level within the
device. The highest layer, other than the device, is the
configuration. A device may have multiple configura-
tions. For example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always a
control endpoint and by default, when the device is on
the bus, Endpoint 0 must be available to configure the
device.
17.10.2
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 17-9 shows an example of a
transaction within a frame.
FIGURE 17-13:
© 2006 Microchip Technology Inc.
LAYERED FRAMEWORK
FRAMES
Endpoint
USB LAYERS
Interface
Endpoint
Endpoint
PIC18F2455/2550/4455/4550
Configuration
Preliminary
Device
17.10.3
There are four transfer types defined in the USB
specification.
• Isochronous: This type provides a transfer
• Bulk: This type of transfer method allows for large
• Interrupt: This type of transfer provides for
• Control: This type provides for device setup
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.
17.10.4
Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an external
source, while bus powered devices use power supplied
from the bus.
Endpoint
method for large amounts of data (up to
1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This is
good for streaming applications where small data
loss is not critical, such as audio.
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
ensured timely delivery for small blocks of data,
plus data integrity is ensured.
control.
To other Configurations (if any)
Interface
TRANSFERS
POWER
Endpoint
To other Interfaces (if any)
DS39632C-page 185

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