PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 416

• Manufacturer Part Number: PIC18F4550-I/PT
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2455/2550/4455/4550
C
C Compilers
CALL ................................................................................ 322
CALLW ............................................................................. 351
Capture (CCP Module) ..................................................... 143
Capture (ECCP Module) .................................................. 150
Capture/Compare (CCP Module)
Capture/Compare/PWM (CCP) ........................................ 141
Clock Sources .................................................................... 31
CLRF ................................................................................ 323
CLRWDT .......................................................................... 323
Code Examples
Code Protection ............................................................... 285
COMF ............................................................................... 324
Comparator ...................................................................... 269
DS39632C-page 414
MPLAB C18 ............................................................. 358
MPLAB C30 ............................................................. 358
CCP Pin Configuration ............................................. 143
CCPRxH:CCPRxL Registers ................................... 143
Prescaler .................................................................. 143
Software Interrupt .................................................... 143
Timer1/Timer3 Mode Selection ................................ 143
Associated Registers ............................................... 145
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 142
CCP2 Pin Assignment ............................................. 142
CCPRxH Register .................................................... 142
CCPRxL Register ..................................................... 142
Compare Mode. See Compare.
Interaction of Two CCP Modules for
Module Configuration ............................................... 142
Effects of Power-Managed Modes ............................. 33
Selecting the 31 kHz Source ...................................... 31
Selection Using OSCCON Register ........................... 31
16 x 16 Signed Multiply Routine ................................ 96
16 x 16 Unsigned Multiply Routine ............................ 96
8 x 8 Signed Multiply Routine .................................... 95
8 x 8 Unsigned Multiply Routine ................................ 95
Changing Between Capture Prescalers ................... 143
Computed GOTO Using an Offset Value ................... 60
Data EEPROM Read ................................................. 91
Data EEPROM Refresh Routine ................................ 92
Data EEPROM Write ................................................. 91
Erasing a Flash Program Memory Row ..................... 84
Fast Register Stack .................................................... 60
How to Clear RAM (Bank 1) Using
Implementing a Real-Time Clock Using a
Initializing PORTA .................................................... 111
Initializing PORTB .................................................... 114
Initializing PORTC .................................................... 117
Initializing PORTD .................................................... 120
Initializing PORTE .................................................... 123
Loading the SSPBUF (SSPSR) Register ................. 196
Reading a Flash Program Memory Word .................. 83
Saving STATUS, WREG and BSR
Writing to Flash Program Memory ....................... 86–87
Analog Input Connection Considerations ................. 273
Associated Registers ............................................... 273
Configuration ............................................................ 270
Effects of a Reset ..................................................... 272
Interrupts .................................................................. 272
Timer Resources .............................................. 142
Indirect Addressing ............................................ 72
Timer1 Interrupt Service .................................. 133
Registers in RAM ............................................. 109
Preliminary
Comparator Specifications ............................................... 375
Comparator Voltage Reference ....................................... 275
Compare (CCP Module) .................................................. 144
Compare (ECCP Module) ................................................ 150
Configuration Bits ............................................................ 286
Configuration Register Protection .................................... 305
Context Saving During Interrupts ..................................... 109
Conversion Considerations .............................................. 410
CPFSEQ .......................................................................... 324
CPFSGT .......................................................................... 325
CPFSLT ........................................................................... 325
Crystal Oscillator/Ceramic Resonator ................................ 25
Customer Change Notification Service ............................ 423
Customer Notification Service ......................................... 423
Customer Support ............................................................ 423
D
Data Addressing Modes .................................................... 72
Data EEPROM
Data EEPROM Memory ..................................................... 89
Data Memory ..................................................................... 63
DAW ................................................................................ 326
DC and AC Characteristics
Operation ................................................................. 271
Operation During Sleep ........................................... 272
Outputs .................................................................... 271
Reference ................................................................ 271
Response Time ........................................................ 271
Accuracy and Error .................................................. 276
Associated Registers ............................................... 277
Configuring .............................................................. 275
Connection Considerations ...................................... 276
Effects of a Reset .................................................... 276
Operation During Sleep ........................................... 276
CCP Pin Configuration ............................................. 144
CCPRx Register ...................................................... 144
Software Interrupt .................................................... 144
Special Event Trigger .............................. 139, 144, 268
Timer1/Timer3 Mode Selection ................................ 144
Special Event Trigger .............................................. 150
Comparing Addressing Modes with the
Direct ......................................................................... 72
Indexed Literal Offset ................................................ 75
Indirect ....................................................................... 72
Inherent and Literal .................................................... 72
Code Protection ....................................................... 305
Associated Registers ................................................. 93
EECON1 and EECON2 Registers ............................. 89
Operation During Code-Protect ................................. 92
Protection Against Spurious Write ............................. 92
Reading ..................................................................... 91
Using ......................................................................... 92
Write Verify ................................................................ 91
Writing ....................................................................... 91
Access Bank .............................................................. 65
and the Extended Instruction Set .............................. 75
Bank Select Register (BSR) ...................................... 63
General Purpose Registers ....................................... 65
Map for PIC18F2455/2550/4455/4550 Devices ......... 64
Special Function Registers ........................................ 66
USB RAM .................................................................. 63
Graphs and Tables .................................................. 399
External Signal ................................................ 271
Internal Signal .................................................. 271
Extended Instruction Set Enabled ..................... 76
Map .................................................................... 66
© 2006 Microchip Technology Inc.