PIC16F1827-I/P Microchip Technology Inc., PIC16F1827-I/P Datasheet
PIC16F1827-I/P
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PIC16F1827-I/P Summary of contents
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... Flash Microcontrollers 2011 Microchip Technology Inc. PIC16(L)F1826/27 with nanoWatt XLP Technology Data Sheet DS41391D ...
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... MCUs and dsPIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. logo, MPLAB, PIC, PICmicro, PICSTART, ® DSCs ® code hopping EE OQ 2011 Microchip Technology Inc. ...
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... In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via two pins • Enhance Low-Voltage Programming • Power-Saving Sleep mode 2011 Microchip Technology Inc. PIC16(L)F1826/27 Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP: • Operating Current: 75 MHz, 1.8V, typical • ...
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... PIC16(L)F1826/27 PIC16(L)F1826/27 Family Types Program Data Memory Memory PIC16LF1826 2K 256 PIC16F1826 2K 256 PIC16LF1827 4K 384 PIC16F1827 4K 384 One pin is input only. Note 1: Pin Diagram – 18-Pin PDIP, SOIC PDIP, SOIC RA5/MCLR/V Pin Diagram – 20-Pin SSOP (PIC16(L)F1826/27) SSOP RA5/MCLR/V DS41391D-page 4 256 16 12 ...
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... Pin Diagram – 28-Pin QFN/UQFN QFN/UQFN RA5/MCLR/V 2011 Microchip Technology Inc. PIC16(L)F1826/27 PIC16(L)F1826/27 PIC16(L)F1826/ RB0 RA7 RA6 RB7 RB6 DS41391D-page 5 ...
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TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1826/27) RA0 AN0 — RA1 AN1 — RA2 AN2 V - REF DACOUT RA3 AN3 V + REF RA4 3 ...
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... Packaging Information.............................................................................................................................................................. 383 Appendix A: Revision History............................................................................................................................................................. 393 Appendix B: Device Differences ........................................................................................................................................................ 393 Index .................................................................................................................................................................................................. 395 The Microchip Web Site ..................................................................................................................................................................... 403 Customer Change Notification Service .............................................................................................................................................. 403 Customer Support .............................................................................................................................................................................. 403 Reader Response .............................................................................................................................................................................. 404 Product Identification System ............................................................................................................................................................ 405 2011 Microchip Technology Inc. PIC16(L)F1826/27 ) ................................................................................................................................ 321 ™ DS41391D-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41391D-page 8 to receive the most current information on all of our products. 2011 Microchip Technology Inc. ...
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... Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2011 Microchip Technology Inc. PIC16(L)F1826/27 of the ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: DS41391D-page 10 Program Flash Memory RAM CPU (Figure 2-1) Timer2- Timer1 DAC Comparators Types Modulator FVR EUSART CapSense EEPROM PORTA PORTB 2011 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16(L)F1827. 3: Default function location. 2011 Microchip Technology Inc. PIC16(L)F1826/27 Input Output Type Type TTL CMOS General purpose I/O. ...
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... USART asynchronous input. ST CMOS USART synchronous data C™ C™ data input/output 2. ST — SPI data input 2. — CMOS SPI data output 1. = Schmitt Trigger input with CMOS levels I Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16(L)F1827. 3: Default function location. 2011 Microchip Technology Inc. PIC16(L)F1826/27 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. ...
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... Functions are only available on the PIC16(L)F1827. 3: Default function location. DS41391D-page 14 Input Output Type Type Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Section 3.4 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16(L)F1826/27 Saving”, for more for more DS41391D-page 15 ...
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... FSR reg Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W reg Timer Brown-out Reset RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
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... Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F1826 PIC16(L)F1827 2011 Microchip Technology Inc. PIC16(L)F1826/27 The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3 ...
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... Program 0800h Memory 7FFFh PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1827 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Rollover to Page 0 Rollover to Page 1 7FFFh 2011 Microchip Technology Inc. ...
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... THE CONSTANT The BRW instruction makes this type of table very sim- ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2011 Microchip Technology Inc. PIC16(L)F1826/27 DS41391D-page 19 ...
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... Table 3-2. For for detailed 3-5. BANKx INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. ...
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... Note 1: second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2011 Microchip Technology Inc. PIC16(L)F1826/27 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...
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... DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-3 and BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM (16 bytes) Table 3-4. 2011 Microchip Technology Inc. ...
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TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh — 08Eh — 10Eh ...
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TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh — — 40Ch 48Ch 50Ch — — 40Dh 48Dh 50Dh — — 40Eh 48Eh ...
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TABLE 3-3: PIC16(L)F1826/27 MEMORY MAP (CONTINUED) BANK16 BANK17 800h 880h 900h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 80Bh 88Bh 90Bh 80Ch 88Ch 90Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 86Fh 8EFh 96Fh 870h ...
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... BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh — FECh FEDh STKPTR FEEh TOSL FEFh TOSH FF0h Common RAM (Accesses 70h – 7Fh) FFFh = Unimplemented data memory locations, read as ‘0’, DS41391D-page 26 2011 Microchip Technology Inc. ...
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... Write Buffer for the upper 7 bits of the Program Counter x8Ah x0Bh or INTCON GIE PEIE x8Bh x = unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 2011 Microchip Technology Inc. PIC16(L)F1826/27 can be Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... SCS1 SCS0 0011 1-00 0011 1-00 LFIOFR HFIOFS 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 — — 2011 Microchip Technology Inc. ...
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... TXSTA CSRC TX9 19Fh BAUDCON ABDOVF RCIDL x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16(L)F1827 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — LATA4 LATA3 LATA2 LATB5 LATB4 ...
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... CCP2M1 CCP2M0 0000 0000 0000 0000 P2DC1 P2DC0 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C1TSEL1 C1TSEL0 0000 0000 0000 0000 — — 2011 Microchip Technology Inc. ...
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... MDCARL MDCLODIS MDCLPOL 39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16(L)F1827 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 DC3B1 DC3B0 CCP3M3 CCP3M2 DC4B1 ...
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... T4CKPS1 T4CKPS0 -000 0000 -000 0000 — — — — — — — — 0000 0000 0000 0000 1111 1111 1111 1111 T6CKPS1 T6CKPS0 -000 0000 -000 0000 — — 2011 Microchip Technology Inc. ...
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... Bank 22 B0Ch — Unimplemented — B6Fh x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16(L)F1827 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 Value on all Value on Bit 1 Bit 0 other POR, BOR Resets — ...
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... Shaded locations are unimplemented, read as ‘0’. PIC16(L)F1827 only. Note 1: DS41391D-page 34 Bit 5 Bit 4 Bit 3 Bit 2 Value on all Value on Bit 1 Bit 0 other POR, BOR Resets — — — — — — — — — — — — — — — — 2011 Microchip Technology Inc. ...
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... Top-of-Stack Low byte TOSL FEFh — Top-of-Stack High byte TOSH x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. PIC16(L)F1827 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — — Z_SHAD — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA 2011 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1826/27 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address Return Address 0x00 or a single interrupt. instruction is executed, the s, or six s and an instructions 2011 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2011 Microchip Technology Inc. PIC16(L)F1826/27 Return Address 0x0F 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41391D-page 40 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF 2011 Microchip Technology Inc. ...
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... SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0x00 0x7F 2011 Microchip Technology Inc. PIC16(L)F1826/ FSRxH Bank Select 0000 0001 0010 1111 Bank 0 Bank 1 Bank 2 ...
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... FIGURE 3-12: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2011 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2011 Microchip Technology Inc. PIC16(L)F1826/27 by device DS41391D-page 43 ...
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... WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled DS41391D-page 44 R/P-1 R/P-1 R/P-1 IESO CLKOUTEN BOREN<1:0> R/P-1 R/P-1 R/P-1 WDTE<1:0> Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase (2) R/P-1 R/P-1/1 CPD bit 8 R/P-1 R/P-1 FOSC<2:0> bit 0 2011 Microchip Technology Inc. ...
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... EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins 2011 Microchip Technology Inc. PIC16(L)F1826/27 DS41391D-page 45 ...
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... For normal device operation, this bit should be maintained as a '1'. DS41391D-page 46 R/P-1 U-1 R/P-1 (2) DEBUG — BORV R/P-1/1 U-1 U-1 Reserved — — Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase R/P-1 R/P-1/1 STVREN PLLEN bit 8 R/P-1 R/P-1 WRT<1:0> bit 0 2011 Microchip Technology Inc. ...
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... See Section 11.5 “User ID, Device ID and Configuration for more information on accessing Word Access” these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27 Memory Programming Specification” (DS41390). 2011 Microchip Technology Inc. PIC16(L)F1826/27 “Write DS41391D-page 47 ...
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... Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration for more information on accessing Word Access” these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. DS41391D-page 48 2011 Microchip Technology Inc. ...
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... Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 DEV<8:0>: Device ID bits Device PIC16F1826 10 0111 100 PIC16F1827 10 0111 101 PIC16LF1826 10 1000 100 PIC16LF1827 10 1000 101 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. ...
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... PIC16(L)F1826/27 NOTES: DS41391D-page 50 2011 Microchip Technology Inc. ...
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... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2011 Microchip Technology Inc. PIC16(L)F1826/27 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low-Power mode (0 MHz to 0 ...
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... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2011 Microchip Technology Inc. ...
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... Configuration Word 1: • High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. PIC16(L)F1826/27 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL Specifications in Section 30.0 2011 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2011 Microchip Technology Inc. PIC16(L)F1826/27 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. 2011 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2011 Microchip Technology Inc. PIC16(L)F1826/27 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...
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... If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 30.0 Specifications”. 2011 Microchip Technology Inc. “Electrical ...
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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2011 Microchip Technology Inc. PIC16(L)F1826/27 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Section 21.0 for more 2011 Microchip Technology Inc. ...
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... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... DS41391D-page 62 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator 2011 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2011 Microchip Technology Inc. PIC16(L)F1826/27 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
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... Output Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41391D-page 64 Oscillator Failure Test Test Failure Detected Test 2011 Microchip Technology Inc. ...
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... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Section 5.2.2.1 “ ...
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... HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41391D-page 66 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional R-0/0 R-0/q LFIOFR HFIOFS bit 0 2011 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources. Legend: 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16(L)F1826/27 NOTES: DS41391D-page 68 2011 Microchip Technology Inc. ...
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... Upon any device Reset, the reference clock module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2011 Microchip Technology Inc. PIC16(L)F1826/27 6.3 Conflicts with the CLKR Pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...
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... OSC DS41391D-page 70 R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR Pin” R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 0 for details. 2011 Microchip Technology Inc. ...
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... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. Legend: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 ...
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... PIC16(L)F1826/27 NOTES: DS41391D-page 72 2011 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2011 Microchip Technology Inc. PIC16(L)F1826/27 PWRT Zero 64 ms LFINTOSC PWRTEN Device Reset DS41391D-page 73 ...
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... V for a DD BOR , the device BORDC Figure 7-2 for more information. Device Operation upon wake- up from Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
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... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC16(L)F1826/27 (1) T PWRT < T PWRT PWRT (1) T ...
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... Upon bringing MCLR high, the device will begin execution immediately (see 3). This is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 7-4 Reset”for Timer configuration. See for more information. Figure 7- 2011 Microchip Technology Inc. ...
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... FIGURE 7-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16(L)F1826/27 T PWRT T MCLR T OST DS41391D-page 77 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2011 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16(L)F1826/27 7-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41391D-page 80 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Register Bit 1 Bit 0 on Page — BORRDY 75 POR BOR 2011 Microchip Technology Inc. ...
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... A block diagram of the interrupt logic is shown in Figure 8-1. FIGURE 8-1: INTERRUPT LOGIC IOCBNx RBx IOCBPx Q4Q1 Q4Q1 2011 Microchip Technology Inc. PIC16(L)F1826/27 Q4Q1 Edge Detect Data bus = Write IOCBFx CK From all other IOCBFx individual pin detectors Q4Q1 To data bus IOCBFx IOCIE IOC interrupt ...
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... The latency for synchronous interrupts instruction cycles. For asynchronous interrupts, the latency instruction cycles, depending on when the interrupt occurs. See and Figure 8.3 for more details. 2011 Microchip Technology Inc. Figure 8-2 ...
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... PC Execute 2 Cycle Instruction at PC Interrupt GIE PC PC-1 PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16(L)F1826/27 Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP FSR ADDR ...
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... INTF is enabled to be set any time during the Q4-Q1 cycles. DS41391D-page (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = 3 Section 30.0 “Electrical 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) , where T = instruction cycle time Specifications””. 2011 Microchip Technology Inc. ...
Page 85
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16(L)F1826/27 DS41391D-page 85 ...
Page 86
... User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 R/W-0/0 INTE IOCIE TMR0IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) R/W-0/0 R-0/0 (1) INTF IOCIF bit 0 2011 Microchip Technology Inc. ...
Page 87
... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
Page 88
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 EEIE BCL1IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets U-0 R/W-0/0 (1) — CCP2IE bit 0 2011 Microchip Technology Inc. ...
Page 89
... Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt bit 0 Unimplemented: Read as ‘0’ This register is only available on PIC16(L)F1827. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 ...
Page 90
... PIC16(L)F1827 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. (1) U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets 2011 Microchip Technology Inc. R/W-0/0 R/W-0/0 BCL2IE SSP2IE bit 0 ...
Page 91
... Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1826/27 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 92
... R/W-0/0 R/W-0/0 U-0 EEIF BCL1IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) should ensure the U-0 R/W-0/0 (1) — CCP2IF bit 0 2011 Microchip Technology Inc. ...
Page 93
... Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ This register is only available on PIC16(L)F1827. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 94
... U-0 R/W/HS-0/0 R/W/HS-0/0 — BCL2IF SSP2IF bit 0 Register Bit 1 Bit 0 on Page INTF IOCIF 86 PS1 PS0 177 TMR2IE TMR1IE 87 (1) — CCP2IE 88 TMR4IE — 89 BCL2IE SSP2IE 90 TMR2IF TMR1IF 91 (1) — CCP2IF 92 TMR4IF — 93 BCL2IF SSP2IF 94 2011 Microchip Technology Inc. ...
Page 95
... Section 17.0 “Digital-to-Analog Con- and verter (DAC) Module” Section 14.0 “Fixed Volt- for more information on these age Reference (FVR)” modules. 2011 Microchip Technology Inc. PIC16(L)F1826/27 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. ...
Page 96
... Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 91 IOCBF1 IOCBF0 134 IOCBN1 IOCBN0 134 IOCBP1 IOCBP0 134 TMR2IE TMR1IE 92 (1) — CCP2IE 93 BCL2IE SSP2IE 95 TMR2IF TMR1IF 96 (1) — CCP2IF 97 BCL2IF SSP2IF WDTPS0 SWDTEN 105 2011 Microchip Technology Inc. ...
Page 97
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16(L)F1826/27 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> WDT Time-out DS41391D-page 97 ...
Page 98
... The TO and PD bits in the STATUS register are changed to indicate the WDT event. See Register 3-1 Mode Active Active Disabled Active Disabled Disabled Section 5.0 “Oscillator for more for more information. WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 99
... If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 100
... Bit 4 Bit 3 Bit 2 IRCF<3:0> — — WDTPS<4:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE<1:0> Register Bit 1 Bit 0 on Page SCS<1:0> SWDTEN 99 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> CPD 44 FOSC<2:0> 2011 Microchip Technology Inc. ...
Page 101
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2011 Microchip Technology Inc. PIC16(L)F1826/27 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 102
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. 2011 Microchip Technology Inc. (Register 4-1) ...
Page 103
... EECON2 ;Write 55h MOVLW 0AAh ; MOVWF EECON2 ;Write AAh BSF EECON1, WR ;Set WR bit to begin write BSF INTCON, GIE ;Enable Interrupts BCF EECON1, WREN ;Disable writes BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done 2011 Microchip Technology Inc. PIC16(L)F1826/27 DS41391D-page 103 ...
Page 104
... Flash ADDR Flash Data INSTR (PC) INSTR( BSF PMCON1,RD executed here executed here RD bit EEDATH EEDATL Register DS41391D-page 104 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here INSTR ( INSTR( INSTR( executed here executed here 2011 Microchip Technology Inc. ...
Page 105
... Erase Block Device (Row) Size/ Boundary PIC16(L)F1826/27 32 words, EEADRL<4:0> = 00000 2011 Microchip Technology Inc. PIC16(L)F1826/27 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair. ...
Page 106
... Initiate read NOP ; Ignored NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS41391D-page 106 (Figure 11-1) (Figure 11-1) 2011 Microchip Technology Inc. ...
Page 107
... Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF. 2011 Microchip Technology Inc. PIC16(L)F1826/27 The following steps should be completed to load the write latches and program a block of program memory. ...
Page 108
... BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES First word of block to be written 14 EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 Buffer Register DS41391D-page 108 EEDATH EEDATA 6 14 EEADRL<4:0> = 00010 Buffer Register Buffer Register Program Memory 0 8 Last word of block to be written 14 14 EEADRL<4:0> = 11111 Buffer Register 2011 Microchip Technology Inc. ...
Page 109
... EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2011 Microchip Technology Inc. PIC16(L)F1826/27 ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Point to program memory ; Not configuration space ; Specify an erase operation ...
Page 110
... Write AAh ; Set WR bit to begin write ; Any instructions here are ignored as processor ; halts to begin write sequence ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts 2011 Microchip Technology Inc. ...
Page 111
... Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1826/27 11.5 User ID, Device ID and Configuration Word Access Instead of accessing program memory or EEPROM data memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the EECON1 register. This is the region that would be pointed to by PC< ...
Page 112
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue DS41391D-page 112 2011 Microchip Technology Inc. ...
Page 113
... Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> Unimplemented bit, read as ‘0’ ...
Page 114
... EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address DS41391D-page 114 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 115
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 116
... Bit 4 Bit 3 Bit 2 FREE WRERR WREN INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 115 101* 113 114 113 113 INTF IOCIF 91 — CCP2IE 93 — CCP2IF 97 2011 Microchip Technology Inc. ...
Page 117
... Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. 2011 Microchip Technology Inc. PIC16(L)F1826/27 FIGURE 12-1: D Write LATx Write PORTx ...
Page 118
... P1D • P1C • CCP1/P1A • TX/CK These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS41391D-page 118 12-2. For this 2011 Microchip Technology Inc. ...
Page 119
... Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 TXCKSEL: Pin Selection bit 0 = TX/CK function is on RB2 1 = TX/CK function is on RB5 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-0/0 R/W-0/0 R/W-0/0 (1) (1) P2BSEL CCP2SEL P1DSEL U = Unimplemented bit, read as ‘ ...
Page 120
... The ANSELA bits default to the Analog Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. DS41391D-page 120 12-3) reads the 2011 Microchip Technology Inc. ...
Page 121
... For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. 2011 Microchip Technology Inc. PIC16(L)F1826/27 (1) DS41391D-page 121 ...
Page 122
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2011 Microchip Technology Inc. ...
Page 123
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2011 Microchip Technology Inc. PIC16(L)F1826/27 U-0 U-0 U-0 — ...
Page 124
... WDTE0 FOSC2 Register Bit 1 Bit 0 on Page ANSA1 ANSA0 123 LATA1 LATA0 122 PS1 PS0 176 RA1 RA0 122 TRISA1 TRISA0 122 — — — 123 Register Bit 9/1 Bit 8/0 on Page BOREN0 CPD 44 FOSC1 FOSC0 2011 Microchip Technology Inc. ...
Page 125
... Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION register. 2011 Microchip Technology Inc. PIC16(L)F1826/27 12.3.3 ANSELB REGISTER The ANSELB register configure the Input mode of an I/O pin to analog. ...
Page 126
... SCL2 (PIC16(L)F1827 only) TX/CK SCK2 (PIC16(L)F1827 only) P1B RB5 RB6 ICSPCLK (Programming) T1OSI P1C CCP2 (PIC16(L)F1827 only) P2A (PIC16(L)F1827 only) RB6 RB7 ICSPDAT (Programming) T1OSO P1D P2B (PIC16(L)F1827 only) RB7 Priority listed from highest to lowest. Note 1: 2011 Microchip Technology Inc. (1) ...
Page 127
... Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is Note 1: return of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-x/x R/W-x/x R/W-x/x RB4 RB3 RB2 U = Unimplemented bit, read as ‘ ...
Page 128
... Value at POR and BOR/Value at all other Resets R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. R/W-1/1 R/W-1/1 WPUB1 WPUB0 bit 0 R/W-1/1 U-0 ANSB1 — bit 0 2011 Microchip Technology Inc. ...
Page 129
... INTEDG PORTB RB7 RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. — Legend: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 ANSB5 ANSB4 ANSB3 LATB5 LATB4 LATB3 TMR0CS TMR0SE PSA ...
Page 130
... PIC16(L)F1826/27 NOTES: DS41391D-page 130 2011 Microchip Technology Inc. ...
Page 131
... R RBx IOCBPx 2011 Microchip Technology Inc. PIC16(L)F1826/27 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of the port expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE interrupt ...
Page 132
... Value at POR and BOR/Value at all other Resets R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2011 Microchip Technology Inc. ...
Page 133
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB TRISB7 TRISB6 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change. 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE ...
Page 134
... PIC16(L)F1826/27 NOTES: DS41391D-page 134 2011 Microchip Technology Inc. ...
Page 135
... CDAFVR<1:0> FVREN Any peripheral requiring the Fixed Reference (See Table 14-1) 2011 Microchip Technology Inc. PIC16(L)F1826/27 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC and CPS is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 136
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition ( Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 R/W-0/0 R/W-0/0 ADFVR<1:0> bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 136 2011 Microchip Technology Inc. ...
Page 137
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16(L)F1826/27 FIGURE 15-1: 15.2 Minimum Operating V ...
Page 138
... PIC16(L)F1826/27 NOTES: DS41391D-page 138 2011 Microchip Technology Inc. ...
Page 139
... DAC FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note 1: See ADCON0 register 2: 2011 Microchip Technology Inc. PIC16(L)F1826/27 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ...
Page 140
... Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 16.2 peri- AD Figure 16-2. specifica- AD Specifications”for Table 16-1 gives examples of appro- , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 141
... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16(L)F1826/ DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) 100 ns (2) 125 ns (2) (2) (2) (2) 200 ns 250 ns ...
Page 142
... The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 143
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16(L)F1826/27 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 144
... ADRESL MOVF ADRESL,W MOVWF RESULTLO A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 145
... Section 17.0 “Digital-to-Analog Converter (DAC) Module” See 2: Section 14.0 “Fixed Voltage Reference (FVR)” See 3: Section 15.0 “Temperature Indicator Module” 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 146
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS (1) - pin REF DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Section 30.0 “Electrical Specifications” R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 (1) for details. 2011 Microchip Technology Inc. ...
Page 147
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 148
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 149
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. PIC16(L)F1826/27 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 150
... V - REF DS41391D-page 150 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Specifications”. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 151
... TRISB6 FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Legend: 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 152
... PIC16(L)F1826/27 NOTES: DS41391D-page 152 2011 Microchip Technology Inc. ...
Page 153
... The value of the individual resistors within the ladder can be found in Section 29.0 Specifications”. 2011 Microchip Technology Inc. PIC16(L)F1826/27 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. ...
Page 154
... FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41391D-page 154 Digital-to-Analog Converter (DAC) V SOURCE + Steps SOURCE - + DACOUT – DACR<4:0> 5 DAC (To Comparator and ADC Modules) DACOUT DACOE Buffered DAC Output 2011 Microchip Technology Inc. ...
Page 155
... DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc. PIC16(L)F1826/27 This is also the method used to output the voltage level from the FVR to an output pin. See “ ...
Page 156
... Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — DACR4 DACR3 DACR2 U-0 R/W-0/0 — DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0 Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 138 — DACNSS 156 DACR1 DACR0 156 2011 Microchip Technology Inc. ...
Page 157
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2011 Microchip Technology Inc. PIC16(L)F1826/27 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 158
... SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41391D-page 158 SRLEN SRQEN S Q SRQ SR (1) Latch R Q SRNQ SRLEN SRNQEN 2011 Microchip Technology Inc. ...
Page 159
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input. Set only, always reads back ‘0’. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/ MHz MHz OSC OSC 39 ...
Page 160
... SR Latch is reset when the C1 Comparator output is high Comparator output has no effect on the reset input of the SR Latch DS41391D-page 160 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2011 Microchip Technology Inc. ...
Page 161
... SRCON0 SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module. 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 SRCLK1 SRCLK0 SRQEN ...
Page 162
... PIC16(L)F1826/27 NOTES: DS41391D-page 162 2011 Microchip Technology Inc. ...
Page 163
... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2011 Microchip Technology Inc. PIC16(L)F1826/27 FIGURE 19- ...
Page 164
... Output of comparator can be frozen during debugging. 3: DS41391D-page 164 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2011 Microchip Technology Inc. ...
Page 165
... FVR Buffer2 3 CxON PCH<1:0> When CxON = 0, the Comparator will produce a ‘0’ at the output Note 1: When CxON = 0, all multiplexer inputs are disconnected. 2: Output of comparator can be frozen during debugging. 3: 2011 Microchip Technology Inc. PIC16(L)F1826/27 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) ...
Page 166
... The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS CxPOL CxOUT 2011 Microchip Technology Inc. ...
Page 167
... Figure Timer1 Block Diagram (Figure 21-1) information. 2011 Microchip Technology Inc. PIC16(L)F1826/27 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. When either edge detector is triggered and its associ- ...
Page 168
... Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. 2011 Microchip Technology Inc. and V . The SS and V . ...
Page 169
... Legend Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 29.0 “Electrical Specifications” 2011 Microchip Technology Inc. PIC16(L)F1826/ 0. (1) LEAKAGE 0. Vss To Comparator DS41391D-page 169 ...
Page 170
... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. DS41391D-page 170 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0 2011 Microchip Technology Inc. ...
Page 171
... Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 172
... ANSA0 123 CxHYS CxSYNC 170 CxNCH1 CxNCH0 171 MC2OUT MC1OUT 171 — DACNSS 156 DACR1 DACR0 156 ADFVR1 ADFVR0 136 INTF IOCIF 86 LATA1 LATA0 122 (1) — CCP2IE 88 (1) — CCP2IF 92 RA1 RA0 122 TRISA1 TRISA0 122 2011 Microchip Technology Inc. ...
Page 173
... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2011 Microchip Technology Inc. PIC16(L)F1826/27 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘ ...
Page 174
... PIC16(L)F1826/27 FIGURE 20-2: BLOCK DIAGRAM OF THE TIMER0 F /4 OSC 0 T0CKI 1 TMR0SE TMR0CS DS41391D-page 174 1 Sync 8-bit Prescaler PSA 8 PS<2:0> 2011 Microchip Technology Inc. Data Bus 8 TMR0 Set Flag bit TMR0IF on Overflow Overflow to Timer1 ...
Page 175
... Section 29.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. 2011 Microchip Technology Inc. PIC16(L)F1826/27 DS41391D-page 175 ...
Page 176
... Bit 2 — — CPSRNG1 CPSRNG0 CPSOUT TMR0IE INTE IOCIE TMR0IF PSA PS2 TRISA5 TRISA4 TRISA3 TRISA2 R/W-1/1 R/W-1/1 PS<2:0> bit 0 Register Bit 1 Bit 0 on Page T0XCS 318 INTF IOCIF 86 PS1 PS0 177 173* TRISA1 TRISA0 122 2011 Microchip Technology Inc. ...
Page 177
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. PIC16(L)F1826/27 • Gate Toggle mode • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...
Page 178
... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN Instruction Clock (F OSC x System Clock (F ) OSC x External Clocking on T1CKI Pin 0 External Clocking on T1CKI Pin 0 Capacitive Sensing Oscillator x internal clock source is selected, the system clock or they can run Clock Source /4) 2011 Microchip Technology Inc. ...
Page 179
... When switching from synchronous to Note: asynchronous operation possible to skip an increment. When switching from asynchronous to synchronous operation possible to produce an additional increment. 2011 Microchip Technology Inc. PIC16(L)F1826/27 21.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
Page 180
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). for timing details. Figure 21-6 for timing 2011 Microchip Technology Inc. ...
Page 181
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16(L)F1826/27 21.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 182
... PIC16(L)F1826/27 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41391D-page 182 2011 Microchip Technology Inc ...
Page 183
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16(L)F1826/27 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Cleared by software DS41391D-page 183 ...
Page 184
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41391D-page 184 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL 2011 Microchip Technology Inc. Cleared by software ...
Page 185
... This bit is ignored. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 186
... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41391D-page 186 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2011 Microchip Technology Inc. ...
Page 187
... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1826/27 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ...
Page 188
... PIC16(L)F1826/27 NOTES: DS41391D-page 188 2011 Microchip Technology Inc. ...
Page 189
... See Figure 22-1 for a block diagram of Timer2/4/6. FIGURE 22-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> 2011 Microchip Technology Inc. PIC16(L)F1826/27 Reset TMRx Output TMRx Postscaler Comparator 1 PRx TxOUTPS<3:0> Sets Flag bit TMRxIF ...
Page 190
... The Timer2/4/6 timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the the output processor is in Sleep mode. the 4-bit Section 25.1 (MSSPx) Module Overview” 2011 Microchip Technology Inc. ...
Page 191
... TMRxON: Timerx On bit 1 = Timerx Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 2011 Microchip Technology Inc. PIC16(L)F1826/27 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 TxCKPS< ...
Page 192
... TMR2ON TMR4ON TMR6ON (1) (1) Register Bit 1 Bit 0 on Page INTF IOCIF 91 TMR2IE TMR1IE 92 TMR2IF TMR1IF 96 — TMR4IE — 94 — TMR4IF — 98 189* 189* 189* T2CKPS1 T2CKPS0 191 T4CKPS1 T4CKPS0 191 T6CKPS1 T6CKPS0 191 189* 189* 189* 2011 Microchip Technology Inc. ...
Page 193
... Reserved * No Channel * Selected 1111 2011 Microchip Technology Inc. PIC16(L)F1826/27 Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...
Page 194
... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 23-1 through Figure 23-5 show timing diagrams of using various synchronization methods. 2011 Microchip Technology Inc. ...
Page 195
... CARH Active Carrier State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State 2011 Microchip Technology Inc. PIC16(L)F1826/27 CARL CARH CARH CARL both CARL both CARL DS41391D-page 195 ...
Page 196
... Active Carrier CARH State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41391D-page 196 CARL CARH CARL CARH 2011 Microchip Technology Inc. CARL CARL ...
Page 197
... The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. 2011 Microchip Technology Inc. PIC16(L)F1826/27 23.11 Operation in Sleep Mode The DSM module is not affected by Sleep mode. The ...
Page 198
... MDBIT must be selected as the modulation source in the MDSRC register for this operation. 2: DS41391D-page 198 R/W-0/0 R-0/0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) U-0 R/W-0/0 — MDBIT bit 0 (2) 2011 Microchip Technology Inc. ...
Page 199
... CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1826/27 U-0 R/W-x/u R/W-x/u — ...
Page 200
... Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. Note 1: DS41391D-page 200 U-0 R/W-x/u R/W-x/u — MDCH<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) 2011 Microchip Technology Inc. R/W-x/u R/W-x/u bit 0 (1) ...