PIC16F1827-I/P Microchip Technology Inc., PIC16F1827-I/P Datasheet - Page 20

• Manufacturer Part Number: PIC16F1827-I/P
• Description: 18 PDIP .300in TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 125 °C
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
3.1.1.2
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete.
ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
3.2
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers
Addressing”
Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
DS41391D-page 20
constants
my_function
;THE PROGRAM MEMORY IS IN W
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
MOVIW 0[FSR1]
3-3):
Data Memory Organization
(FSR).
Indirect Read with FSR
for more information.
LOW constants
FSR1L
HIGH constants
FSR1H
Example 3-2
ACCESSING PROGRAM
MEMORY VIA FSR
See
;Index0 data
;Index1 data
Section 3.5
demonstrates access-
“Indirect
3.2.1
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in
information, see
TABLE 3-2:
CORE REGISTERS
x0Ah or x8Ah
x0Bh or x8Bh
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
Addresses
Table
CORE REGISTERS
3-5.
 2011 Microchip Technology Inc.
Table
STATUS
PCLATH
INTCON
BANKx
FSR0H
FSR1H
FSR0L
FSR1L
WREG
INDF0
INDF1
3-2. For for detailed
BSR
PCL