PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 110

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
TABLE 9-11:
TABLE 9-12:
DS39682B-page 108
PORTE
LATE
TRISE
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Legend:
Name
(1)
(1)
Pin
(1)
These registers are not available in 28-pin devices.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Bit 7
IBF
—
—
—
PORTE I/O SUMMARY
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Function
RE0
AN5
RE1
AN6
RE2
AN7
WR
RD
CS
Bit 6
OBF
—
—
—
Setting
TRIS
0
1
1
1
0
1
1
1
0
1
1
1
VCFG1
IBOV
Bit 5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
—
—
Type
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
PSPMODE
VCFG0
Preliminary
Bit 4
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 7; default input configuration on POR.
PCFG3
Bit 3
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE2
PCFG2
Bit 2
RE2
Description
TRISE1
PCFG1
Bit 1
© 2006 Microchip Technology Inc.
RE1
TRISE0
PCFG0
Bit 0
RE0
on page
Values
Reset
46
46
46
44