PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 147

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.0
15.1
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I
The I
hardware:
• Master mode
• Multi-Master mode
• Slave mode
PIC18F24J10/25J10 (28-pin) devices have one MSSP
module designated as MSSP1. PIC18F44J10/45J10
(40/44-pin) devices have two MSSP modules,
designated as MSSP1 and MSSP2. Each module
operates independently of the other.
15.2
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and
SSPxCON2). The use of these registers and their indi-
vidual configuration bits differ significantly depending
on whether the MSSP module is operated in SPI or I
mode.
Additional details are provided under the individual
sections.
© 2006 Microchip Technology Inc.
- Full Master mode
- Slave mode (with general address call)
Note:
Note:
2
two
C interface supports the following modes in
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Master SSP (MSSP) Module
Overview
Control Registers
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a particular module, when required.
Control bit names are not individuated.
In devices with more than one MSSP
module, it is very important to pay close
attention to SSPCON register names.
SSP1CON1 and
different operational aspects of the same
module,
SSP2CON1 control the same features for
two different modules.
control
registers
while
2
C™)
SSP1CON2 control
SSP1CON1
(SSPxCON1
and
and
Preliminary
2
C
PIC18F45J10 FAMILY
15.3
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes
communication, typically three pins are used:
• Serial Data Out (SDOx) – RC5/SDO1 or
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RA5/AN4/SS1/C2OUT or
Figure 15-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 15-1:
Note: Only port I/O names are used in this diagram for
RD2/PSP2/SDO2
RD1/PSP1/SDI2/SDA2
RD0/PSP0/SCK2/SCL2
RD3/PSP3/SS2
RC3 or RD0
RC4 or RD1
RC5 or RD2
RA5 or RD3
the sake of brevity. Refer to the text for a full list
of multiplexed functions.
SPI Mode
of
SPI
Read
are
SSx Control
Enable
Select
SMP:CKE
Edge
MSSP BLOCK DIAGRAM
(SPI™ MODE)
bit 0
Select
Edge
supported.
SSPxBUF reg
TRIS bit
Data to TX/RX in SSPxSR
SSPxSR reg
2
SSPM3:SSPM0
Clock Select
4
2
DS39682B-page 145
(
Prescaler
To
4, 16, 64
TMR2 Output
Write
Clock
Shift
Data Bus
accomplish
Internal
2
T
OSC
)