PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 160

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F45J10 FAMILY
REGISTER 15-5:
DS39682B-page 158
bit 2
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 1
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit (Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by
0 = Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Legend:
R = Readable bit
-n = Value at POR
R/W-0
GCEN
Note:
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
Automatically cleared by hardware.
hardware.
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
these bits may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
ACKSTAT
R/W-0
ACKDT
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
2
C
ACKEN
R/W-0
(1)
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RCEN
(1)
R/W-0
2
C™ MODE)
(1)
2
C module is not in the Idle mode,
PEN
R/W-0
(1)
© 2006 Microchip Technology Inc.
(1)
x = Bit is unknown
RSEN
(1)
R/W-0
(1)
SEN
R/W-0
bit 0
(1)