PIC18F45J10-I/ML Microchip Technology Inc., PIC18F45J10-I/ML Datasheet - Page 123

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: 44 PIN, 32 KB FLASH, 1024 RAM
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F45J10-I/ML

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin QFN
• Programmable Memory: 32K Bytes
• Ram Size: 1K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 2-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.0
The Timer2 timer module incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
• Readable and writable (both registers)
• Software programmable prescaler
• Software programmable postscaler
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the
The module is controlled through the T2CON register
(Register 12-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 12-1.
REGISTER 12-1:
© 2006 Microchip Technology Inc.
respectively)
(1:1, 1:4 and 1:16)
(1:1 through 1:16)
MSSP module
TIMER2 MODULE
bit 7
bit 6-3
bit 2
bit 1-0
T2CON: TIMER2 CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
U-0
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
R/W-0
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
PIC18F45J10 FAMILY
12.1
In normal operation, TMR2 is incremented from 00h on
each clock (F
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options; these are selected by
the prescaler
(T2CON<1:0>). The value of TMR2 is compared to that
of the period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the
“Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
TMR2 is not cleared when T2CON is written.
Watchdog Timer Reset or Brown-out Reset)
output
Timer2 Operation
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OSC
counter/postscaler
control
/4). A 4-bit counter/prescaler on the
R/W-0
bits,
x = Bit is unknown
R/W-0
T2CKPS1:T2CKPS0
(see
DS39682B-page 121
Section 12.2
R/W-0
bit 0