DSPIC30F4011-30I/P Microchip Technology Inc., DSPIC30F4011-30I/P Datasheet - Page 122

• Manufacturer Part Number: DSPIC30F4011-30I/P
• Description: 16 BIT MCU/DSP 40LD 30MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4011-30I/P

• A/d Inputs: 9-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 40-pin PDIP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F
17.12.3
In I
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock arbi-
tration is taking place, for instance, the BRG is reloaded
when the SCL pin is sampled high.
As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 17-1:
17.12.4
Clock arbitration occurs when the master de-asserts
the SCL pin (SCL allowed to float high) during any
receive, transmit, or Restart/Stop condition. When the
SCL pin is allowed to float high, the baud rate generator
(BRG) is suspended from counting until the SCL pin is
actually sampled high. When the SCL pin is sampled
high, the baud rate generator is reloaded with the con-
tents of I2CBRG and begins counting. This ensures
that the SCL high time will always be at least one BRG
rollover count in the event that the clock is held low by
an external device.
17.12.5
Multi-Master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a 1 on SDA, by letting SDA float high
while another master asserts a 0. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 1 and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The mas-
ter will set the MI2CIF pulse and reset the master por-
tion of the I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted, and a
value can now be written to I2CTRN. When the user
services the I
tine, if the I
can resume communication by asserting a Start
condition.
DS70082G-page 120
2
C Master mode, the reload value for the BRG is
I2CBRG =
2
2
BAUD RATE GENERATOR
CLOCK ARBITRATION
MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
C port to its Idle state.
C bus is free (i.e., the P bit is set) the user
2
2
C standard, F
C master event Interrupt Service Rou-
(
F
F
SCL
SERIAL CLOCK RATE
CY
–
SCL
1,111,111
may be 100 kHz or
F
CY
)
– 1
Preliminary
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are de-asserted,
and the respective control bits in the I2CCON register
are cleared to 0. When the user services the bus colli-
sion Interrupt Service Routine, and if the I
the user can resume communication by asserting a
Start condition.
The Master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.
A write to the I2CTRN will start the transmission of data
at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
In a Multi-Master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
17.13 I
17.13.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission, and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
17.13.2
For the I
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
2
Sleep and Idle Modes
2
C, the I2CSIDL bit selects if the module will
C Module Operation During CPU
I
SLEEP MODE
I
MODE
2
2
C OPERATION DURING CPU
C OPERATION DURING CPU IDLE
 2004 Microchip Technology Inc.
2
C bus is free,
2
C