DSPIC30F4011-30I/P Microchip Technology Inc., DSPIC30F4011-30I/P Datasheet - Page 75

• Manufacturer Part Number: DSPIC30F4011-30I/P
• Description: 16 BIT MCU/DSP 40LD 30MIPS 48 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F4011-30I/P

• A/d Inputs: 9-Channels, 10-Bit
• Comparators: 4
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: CAN, I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 40-pin PDIP
• Programmable Memory: 48K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.0
This section describes the 16-bit General Purpose
(GP) Timer1 module and associated operational
modes. Figure 9-1 depicts the simplified block diagram
of the 16-bit Timer1 Module.
The following sections provide a detailed description,
including setup and control registers along with associ-
ated block diagrams for the operational modes of the
timers.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free running interval timer/counter. The 16-bit timer has
the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
• Timer gate operation
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
• Interrupt on 16-bit period register match or falling
FIGURE 9-1:
 2004 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046).
modes
edge of external gate signal
TIMER1 MODULE
SOSCO/
SOSCI
T1CK
T1IF
Event Flag
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TGATE
0
1
Reset
Equal
LPOSCEN
Comparator x 16
TMR1
PR1
Preliminary
Q
Q
Gate
Sync
CK
T
CY
D
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the period register PR1, then
resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous mode
of operation and the CPU goes into the Idle mode, the
timer will stop incrementing if TSIDL = 1.
TGATE
1 X
0 0
0 1
TON
(3)
TSYNC
0
1
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Sync
2
dsPIC30F
DS70082G-page 73