ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 26

• Manufacturer Part Number: ICS1893YI-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1893YI-10LF

5.1 MII Data Interface
ICS1893Y-10 Rev F 1/20/04
The most common configuration for an ICS1893Y-10’s MAC/Repeater Interface is the Medium
Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. When the ICS1893Y-10
MAC/Repeater Interface is configured for the MII Data Interface mode, data is transferred between the
PHY and the MAC/repeater as framed, 4-bit parallel nibbles. In addition, the interface also provides status
and control signals to synchronize the transfers.
The ICS1893Y-10 provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a
transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles).
•
•
Both the MII transmit clock and the MII receive clock are provided to the MAC/Reconciliation sublayer by
the ICS1893Y-10 (that is, the ICS1893Y-10 sources the TXCLK and RXCLK signals to the MAC/repeater).
Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL).
The ICS1893Y-10 is fully compliant with these definitions and sources both of these signals to the
MAC/repeater. When operating in:
•
•
As mentioned in
That is, it is possible to connect its MII to a MAC when power is already applied to the MAC. To support this
functionality, the ICS1893Y-10 isolates its MII signals and tri-states the signals on all Twisted-Pair Transmit
pins (TP_TXP and TP_TXN) during a power-on reset. Upon completion of the reset process, the
ICS1893Y-10 enables its MII and enables its Twisted-Pair Transmit signals.
The ICS1893Y-10’s MII transmit data path includes the following:
The ICS1893Y-10’s MII receive data path includes the following:
Half-duplex mode, the ICS1893Y-10 asserts the Carrier Sense signal when data is being either
transmitted or received. While operating in half-duplex mode, the ICS1893Y-10 also asserts its Collision
Detect signal to indicate that data is being received while a transmission is in progress.
Full-duplex mode, the ICS1893Y-10 asserts the Carrier Sense signal only when receiving data and
forces the Collision Detect signal to remain inactive.
– A data nibble, TXD[3:0]
– A transmit data clock to synchronize transfers, TXCLK
– A transmit enable signal, TXEN
– A transmit error signal, TXER
– A separate data nibble, RXD[3:0]
– A receive data clock to synchronize transfers, RXCLK
– A receive data valid signal, RXDV
– A receive error signal, RXER
ICS1893Y-10 Data Sheet - Release
Section 4.1.1.3, “Hot
Copyright © 2004, Integrated Circuit Systems, Inc.
Insertion”, the ICS1893Y-10 design allows hot insertion of its MII.
All rights reserved.
26
Chapter 5 Interface Overviews
January, 2004