ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet
ICS1893YI-10LF
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ICS1893YI-10LF Summary of contents
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Integrated Circuit Systems, Inc. 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™ General The ICS1893Y- low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893Y-10 architecture is based on the ICS1892. The ...
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ICS1893Y-10 Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 13 Chapter 2 Conventions and Nomenclature..................................................................................... 15 Chapter 3 Overview of the ICS1893Y-10 .......................................................................................... 17 3.1 100Base-TX Operation ..........................................................................................18 3.2 10Base-T Operation ...............................................................................................18 Chapter ...
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ICS1893Y-10 - Release Section 6.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................46 6.3.1 PCS Sublayer ........................................................................................................46 6.3.2 PMA Sublayer ........................................................................................................46 6.3.3 PCS/PMA Transmit Modules .................................................................................47 6.3.4 PCS/PMA Receive Modules ..................................................................................48 6.3.5 PCS Control Signal Generation .............................................................................49 6.3.6 4B/5B Encoding/Decoding ...
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ICS1893Y-10 Data Sheet - Release Section Chapter 7 Management Register Set ............................................................................................... 61 7.1 Introduction to Management Register Set .............................................................62 7.1.1 Management Register Set Outline .........................................................................62 7.1.2 Management Register Bit Access ..........................................................................63 7.1.3 Management Register Bit Default Values ..............................................................63 7.1.4 ...
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ICS1893Y-10 - Release Section 7.5 Register 3: PHY Identifier Register ........................................................................76 7.5.1 OUI bits 19-24 (bits 3.15:10) ..................................................................................76 7.5.2 Manufacturer’s Model Number (bits 3.9:4) .............................................................76 7.5.3 Revision Number (bits 3.3:0) .................................................................................77 7.6 Register 4: Auto-Negotiation Register ...................................................................77 7.6.1 Next Page ...
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ICS1893Y-10 Data Sheet - Release Section 7.11 Register 16: Extended Control Register ................................................................89 7.11.1 Command Override Write Enable (bit 16.15) .........................................................90 7.11.2 ICS Reserved (bits 16.14:11) .................................................................................90 7.11.3 PHY Address (bits 16.10:6) ...................................................................................90 7.11.4 Stream Cipher Scrambler Test Mode (bit ...
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ICS1893Y-10 - Release Section 7.14 Register 19: Extended Control Register 2 ...........................................................100 7.14.1 Node/Repeater Configuration (bit 19.15) .............................................................101 7.14.2 Hardware/Software Priority Status (bit 19.14) ......................................................101 7.14.3 Remote Fault (bit 19.13) ......................................................................................101 7.14.4 ICS Reserved (bits 19.12:8) .................................................................................101 7.14.5 Twisted Pair ...
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ICS1893Y-10 Data Sheet - Release Section 9.5.10 10M Serial Interface: Transmit Latency ...............................................................134 9.5.11 10M Media Independent Interface: Transmit Latency ..........................................135 9.5.12 MII / 100M Stream Interface: Transmit Latency ...................................................136 9.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) ...............137 9.5.14 10M ...
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ICS1893Y-10 - Release Revision History • The initial release of this document, Rev A, was dated August 5, 1999. • Rev B was dated September 10, 1999. The following list also indicates what changes were made. – Page 1. Document ...
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ICS1893Y-10 Data Sheet - Release • This release of this document, Rev C, is dated May 22, 2000. Change bars indicate where all changes are made. (For an explanation of change bars, see the Change Bar note on this page.) ...
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ICS1893Y-10 - Release • This release of this document, Rev D, is dated 6 March 2003. The following list indicates where changes occur. – Table of Contents reflect page renumbering. – Table 7-10, changed “Decimal” revision number from 0 to ...
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ICS1893Y-10 Data Sheet - Release • This release of this document, Rev F, is dated 20 January 2004. The following list indicates where changes occur. – Table of Contents reflect page renumbering. – Table 8-18 to correct Bit 17.3 definition ...
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ICS1893Y-10 - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute ...
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ICS1893Y-10 Data Sheet - Release Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893Y- physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ...
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ICS1893Y-10 - Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or signal) names Registers ICS1893Y-10 ...
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ICS1893Y-10 Data Sheet - Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1893Y-10 Rev F 1/20/04 Convention / Nomenclature • When referring to ...
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ICS1893Y-10 - Release Chapter 3 Overview of the ICS1893Y-10 The ICS1893Y- stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control)/Repeater Interface, converts them into a serial bit stream, encodes them, and transmits ...
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ICS1893Y-10 Data Sheet - Release 3.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893Y-10 accepts packets from a MAC/repeater and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893Y-10 encapsulates each MAC/repeater frame, including the ...
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ICS1893Y-10 - Release Chapter 4 Operating Modes Overview The ICS1893Y-10 operating modes and interfaces are configurable with one of two methods. The HW/SW (hardware/software) pin determines which method the ICS1893Y- use, either its hardware pins or its register ...
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ICS1893Y-10 Data Sheet - Release 4.1 Reset Operations This section first discusses reset operations in general and then specific ways in which the ICS1893Y-10 can be configured for various reset options. 4.1.1 General Reset Operations The following reset operations apply ...
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ICS1893Y-10 - Release 4.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893Y-10 can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893Y-10) • Software reset (using Control ...
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ICS1893Y-10 Data Sheet - Release 4.1.2.3 Software Reset Entering Software Reset Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit 0.15. When this write occurs, the ICS1893Y-10 enters the reset state ...
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ICS1893Y-10 - Release 4.3 Automatic Power-Saving Operations The ICS1893Y-10 has power-saving features that automatically minimize its total power consumption while it is operating. Table 4-1 lists the ICS1893Y-10 automatic power-saving features for the various modes. Table 4-1. Automatic Power-Saving Features, ...
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ICS1893Y-10 Data Sheet - Release 4.5 100Base-TX Operations The ICS1893Y-10 100Base-TX mode provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893Y- 100M translator between a MAC/repeater and the ...
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ICS1893Y-10 - Release Chapter 5 Interface Overviews The ICS1893Y-10 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, ...
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ICS1893Y-10 Data Sheet - Release 5.1 MII Data Interface The most common configuration for an ICS1893Y-10’s MAC/Repeater Interface is the Medium Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. When the ICS1893Y-10 MAC/Repeater Interface is configured for ...
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ICS1893Y-10 - Release 5.2 100M Symbol Interface The 100M Symbol Interface has a primary objective of supporting 100Base-TX repeater applications for which the repeater requires only recovered parallel data and for which the repeater provides all the necessary framing and ...
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ICS1893Y-10 Data Sheet - Release Table 5-1 lists the pin mappings for the ICS1893Y-10 100M Symbol Interface mode. Table 5-1. Pin Mappings for 100M Symbol Interface Mode Default 10M / 100M MII Pin Names COL No connect. [Because the MAC/repeater ...
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ICS1893Y-10 - Release 5.3 10M Serial Interface When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1893Y-10 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ...
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ICS1893Y-10 Data Sheet - Release Table 5-2 lists the pin mappings for the ICS1893Y-10 10M Serial Interface mode. Table 5-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS MDC MDC ...
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ICS1893Y-10 - Release 5.4 Serial Management Interface The ICS1893Y-10 provides an ISO/IEC compliant, two-wire Serial Management Interface as part of its MAC/Repeater Interface. This Serial Management Interface is used to exchange control, status, and configuration information between a Station Management ...
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ICS1893Y-10 Data Sheet - Release 5.5.1 Twisted-Pair Transmitter Interface The twisted-pair transmitter driver uses an H-bridge configuration, which requires that the transmit transformer not have a choke on the chip side. ICS suggests any of the following for the H-bridge: ...
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ICS1893Y-10 - Release 5.5.2 Twisted-Pair Receiver Interface Figure 5-2 shows the design for the ICS1893Y-10 twisted-pair receiver interface. Two 56.2 Ω 1% resistors are in series, with the center bypassed to ground with a 0.1- µ F bypass • capacitor. ...
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ICS1893Y-10 Data Sheet - Release 5.6 Clock Reference Interface The REF_IN pin provides the ICS1893Y-10 Clock Reference Interface. The ICS1893Y-10 requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to ...
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ICS1893Y-10 - Release If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893Y-10. A pair of bypass capacitors on either side of the crystal are ...
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ICS1893Y-10 Data Sheet - Release 5.7 Configuration Interface The following Configuration and Status Interface pins allow the ICS1893Y- completely configured and controlled in hardware mode: • 10/100SEL • ANSEL • DPXSEL • HW/SW • MII/SI • NOD/REP • ...
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ICS1893Y-10 - Release 5.8 Status Interface The ICS1893Y-10 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking Status. In addition, as listed in that report the results of continual link monitoring by providing signals ...
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ICS1893Y-10 Data Sheet - Release Figure 5-4 shows typical biasing and LED connections for the ICS1893Y-10. Figure 5-4. ICS1893Y-10 LED - PHY Address P4RD P3TD 64 62 REC TRANS 10K Ω 10K Ω This circuit decodes to PHY address = ...
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ICS1893Y-10 - Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893Y-10 functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA Sublayers” • ...
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ICS1893Y-10 Data Sheet - Release 6.1 Functional Block: Media Independent Interface All ICS1893Y-10 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893Y-10 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) ...
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ICS1893Y-10 - Release 6.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893Y-10 has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end of the link segment’s ...
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ICS1893Y-10 Data Sheet - Release 6.2.1 Auto-Negotiation General Process The Auto-Negotiation sublayer uses a physical signaling technique that is transparent at the packet level and all higher protocol levels. This technique builds on the link pulse mechanism employed in 10Base-T ...
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ICS1893Y-10 - Release 6.2.2 Auto-Negotiation: Parallel Detection The ICS1893Y-10 supports parallel detection therefore compatible with networks that do not support the auto-negotiation process. When enabled, the Auto-Negotiation sublayer can detect legacy 10Base-T link partners as well as 100Base-TX ...
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ICS1893Y-10 Data Sheet - Release 6.2.4 Auto-Negotiation: Reset and Restart If enabled, execution of the ICS1893Y-10 auto-negotiation process occurs at power-up and upon management request. There are two primary ways to begin the Auto-Negotiation state machine: • ICS1893Y-10 reset • ...
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ICS1893Y-10 - Release successfully established, either through auto-negotiation or parallel detection. The STA can then poll the Auto-Negotiation Link Partner Ability Register and determine the highest-performance operating mode in common with the capabilities it is advertising. The ISO/IEC-defined priority table ...
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ICS1893Y-10 Data Sheet - Release 6.3 Functional Block: 100Base-X PCS and PMA Sublayers The ICS1893Y-10 is fully compliant with clause 24 of the ISO/IEC specification, which defines the 100Base-X Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 6.3.1 ...
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ICS1893Y-10 - Release 6.3.3 PCS/PMA Transmit Modules Both the PCS and PMA sublayers have Transmit modules. 6.3.3.1 PCS Transmit Module The ICS1893Y-10 PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts the nibbles into 5-bit ‘code groups’ (referred ...
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ICS1893Y-10 Data Sheet - Release 6.3.4 PCS/PMA Receive Modules Both the PCS and PMA sublayers have Receive modules. 6.3.4.1 PCS Receive Module The ICS1893Y-10 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA ...
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ICS1893Y-10 - Release 6.3.5 PCS Control Signal Generation For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The CRS control signals is generated as follows: 1. When a logic ...
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ICS1893Y-10 Data Sheet - Release 6.4 Functional Block: 100Base-TX TP-PMD Operations The ICS1893Y-10 supports both 10Base-T and 100Base-TX operations. For 100Base-TX operations, the TP-PMD module performs stream-cipher scrambling/descrambling and MLT-3 encoding/decoding (3-level, multi-level transition) in compliance with the ANSI Standard ...
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ICS1893Y-10 - Release 6.4.4 100Base-TX Operation: Adaptive Equalizer The ICS1893Y-10 has a TP-PMD sublayer that uses adaptive equalization circuitry to compensate for signal amplitude and phase distortion incurred from the transmission medium data rate of 100 Mbps, the ...
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ICS1893Y-10 Data Sheet - Release 6.4.7 100Base-TX Operation: Auto Polarity Correction The ICS1893Y-10 can sense and then automatically correct a signal polarity that is reversed on its Twisted-Pair Receiver inputs. A signal polarity reversal occurs when the input signals on ...
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ICS1893Y-10 - Release 6.5 Functional Block: 10Base-T Operations When configured for 10Base-T mode, the ICS1893Y-10 MAC/Repeater Interface can be configured to provide either a 10M MII (Media Independent Interface 10M Serial Interface. The Twisted-Pair Interface is automatically configured ...
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ICS1893Y-10 Data Sheet - Release begin with reception of the MAC Frame Preamble and continue as long as the ICS1893Y-10 is receiving data. 6.5.4 10Base-T Operation: Idle An ICS1893Y-10 transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI ...
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ICS1893Y-10 - Release Note ICS1893Y-10 receives ‘valid data’ when its Twisted-Pair Receiver phase-locked loop can acquire lock and extract the receive clock from the incoming data stream for a minimum of three consecutive bit times. 2. When a ...
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ICS1893Y-10 Data Sheet - Release 6.5.9 10Base-T Operation: Jabber The ICS1893Y-10 has an ISO/IEC compliant Jabber Detection Function that, when enabled, monitors the data stream sent to its Twisted-Pair Transmitter to ensure that it does not exceed the 10Base-T Jabber ...
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ICS1893Y-10 - Release 6.5.11 10Base-T Operation: Twisted-Pair Transmitter The 10Base-T Twisted-Pair Transmitter is functionally similar to the 100Base-TX Twisted-Pair Transmitter. The primary differences are in the data rate and signaling, as specified in the ISO/IEC specifications. For more information, see ...
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ICS1893Y-10 Data Sheet - Release 6.6 Functional Block: Management Interface As part of the MAC/Repeater Interface, the ICS1893Y-10 provides a two-wire serial management interface which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used to ...
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ICS1893Y-10 - Release 6.6.2.1 Management Frame Preamble The ICS1893Y-10 continually monitors its serial management interface for either valid data or a Management Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6. When the MF Preamble ...
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ICS1893Y-10 Data Sheet - Release 6.6.2.7 Management Frame Turnaround A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the REGAD field and the Data field. This time allows an ICS1893Y-10 and an STA ...
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ICS1893Y-10 - Release Chapter 7 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA Read/Write Access ...
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ICS1893Y-10 Data Sheet - Release 7.1 Introduction to Management Register Set This section explains in general terms the Management Register set discussed in this chapter. (For a summary of the Management Register set, see 7.1.1 Management Register Set Outline This ...
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ICS1893Y-10 - Release 7.1.2 Management Register Bit Access The ICS1893Y-10 Management Registers include one or more of the following types of bits: Table 7-3. Description of Management Register Bit Types Management Register Bit Types Symbol Read-Only Command Override Write Read/Write ...
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ICS1893Y-10 Data Sheet - Release 7.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 7.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to record an ...
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ICS1893Y-10 - Release 7.2 Register 0: Control Register Table 7-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes of the ICS1893Y-10. • The Control Register is accessible through the MII Management ...
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ICS1893Y-10 Data Sheet - Release 7.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893Y-10. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling the Twisted-Pair ...
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ICS1893Y-10 - Release 7.2.5 Low Power Mode (bit 0.11) This bit provides one way to control the ICS1893Y-10 low-power mode function. When bit 0.11 is logic: • Zero, there is no impact to ICS1893Y-10 operations. • One, the ICS1893Y-10 enters ...
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ICS1893Y-10 Data Sheet - Release 7.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893Y-10 Duplex Mode. Its operation depends on several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). ...
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ICS1893Y-10 - Release 7.3 Register 1: Status Register Table 7-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893Y-10 and an STA. There are two types of status bits: some report the capabilities ...
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ICS1893Y-10 Data Sheet - Release 7.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893Y-10 can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893Y-10 must set bit 1.14 to logic: • ...
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ICS1893Y-10 - Release 7.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893Y-10 returns a logic zero. • Writes a reserved bit, the STA must use ...
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ICS1893Y-10 Data Sheet - Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893Y-10 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ...
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ICS1893Y-10 - Release 7.3.11 Link Status (bit 1.2) The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit 17. determine if an established link is dropped, even momentarily. To indicate a ...
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ICS1893Y-10 Data Sheet - Release 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893Y-10 - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each ...
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ICS1893Y-10 Data Sheet - Release 7.5 Register 3: PHY Identifier Register Table 7-9 lists the bits for PHY Identifier Register (Register 3), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC ...
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ICS1893Y-10 - Release 7.5.3 Revision Number (bits 3.3:0) Table 7-10 lists the valid ICS1893Y-10 revision numbers, which are 4-bit binary numbers stored in bits 3.3:0. Table 7-10. ICS1893Y-10 Revision Number Decimal Bits 3.3:0 1 0001 7.6 Register 4: Auto-Negotiation Register ...
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ICS1893Y-10 Data Sheet - Release 7.6.1 Next Page (bit 4.15) This bit indicates whether the ICS1893Y-10 uses the Next Page Mode functions during the auto-negotiation process. If bit 4.15 is logic: • Zero, then the ICS1893Y-10 indicates to its remote ...
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ICS1893Y-10 - Release 7.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893Y-10 transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine the specific ...
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ICS1893Y-10 Data Sheet - Release 7.6.5.2 Technology Ability Field: Software Mode In Software mode (that is, the HW/SW pin is logic one), these TAF bits are Command Override Write bits. The default value of these bits depends on the signal ...
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ICS1893Y-10 - Release 7.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 7-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link partner. During ...
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ICS1893Y-10 Data Sheet - Release 7.7.2 Acknowledge (bit 5.14) The ISO/IEC specification defines bit 5.14 as the Acknowledge bit. When this bit is a: • Zero, it indicates that the remote link partner has not received the ICS1893Y-10 Link Control ...
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ICS1893Y-10 - Release 7.8 Register 6: Auto-Negotiation Expansion Register Table 7-13 lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the Auto-Negotiation process. Note: For an explanation of acronyms used in Table 7-13. Auto-Negotiation Expansion Register ...
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ICS1893Y-10 Data Sheet - Release 7.8.2 Parallel Detection Fault (bit 6.4) The ICS1893Y-10 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893Y-10 cannot disseminate the technology being ...
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ICS1893Y-10 - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page ...
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ICS1893Y-10 Data Sheet - Release 7.9.1 Next Page (bit 7.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next ...
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ICS1893Y-10 - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is ...
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ICS1893Y-10 Data Sheet - Release 7.10.1 Next Page (bit 8.15) This bit is used by a PHY/STA to enable the transmission of Next Pages following the base Link Control Word as long as the remote link partner supports the Next ...
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ICS1893Y-10 - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893Y-10 provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of ...
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ICS1893Y-10 Data Sheet - Release 7.11.1 Command Override Write Enable (bit 16.15) The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write (CW) bits located throughout the MII Register set. A two-step process ...
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ICS1893Y-10 - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893Y-10 to transmit symbols that are typically classified as invalid. The purpose of this test bit is to ...
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ICS1893Y-10 Data Sheet - Release 7.12 Register 17: Quick Poll Detailed Status Register Table 7-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed status of ...
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ICS1893Y-10 - Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893Y-10 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the ...
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ICS1893Y-10 Data Sheet - Release If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State Machine achieves. That is, they are updated only if the binary value of the next state is greater than the ...
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ICS1893Y-10 - Release 7.12.6 False Carrier (bit 17.8) The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893Y-10 in 100Base mode. A False Carrier occurs when the ICS1893Y-10 begins evaluating potential data on ...
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ICS1893Y-10 Data Sheet - Release If this bit is set to a logic: • Zero, it indicates a Premature End condition has not been detected since either the last read or reset of this register. • One, it indicates a ...
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ICS1893Y-10 - Release 7.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893Y-10 activity while the ICS1893Y-10 is operating in 10Base-T mode. Note: 1. For an explanation of ...
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ICS1893Y-10 Data Sheet - Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893Y-10 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the ...
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ICS1893Y-10 - Release 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893Y-10 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state ...
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ICS1893Y-10 Data Sheet - Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893Y-10 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to ...
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ICS1893Y-10 - Release 7.14.1 Node/Repeater Configuration (bit 19.15) The Node/Repeater Configuration bit directly indicates the state of the NOD/REP input pin. When this bit is logic: • Zero, the NOD/REP input pin is pulled down, which instructs the operation code ...
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ICS1893Y-10 Data Sheet - Release 7.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893Y-10 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to ...
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ICS1893Y-10 - Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893Y-10 Pin Diagram NOD/REP 1 10/100SEL 2 TP_CT 3 VSS 4 TP_TXP 5 TP_TXN 6 VDD 7 VDD 8 10TCSR 9 100TCSR 10 VSS 11 VSS 12 TP_RXP 13 ...
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ICS1893Y-10 Data Sheet - Release 8.2 ICS1893Y-10 Pin Listings Table 8-1 lists the ICS1893Y-10 pins by pin number. Table 8-1. ICS1893Y-10 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 TP_CT 4 VSS 5 TP_TXP 6 ...
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ICS1893Y-10 - Release 8.3 ICS1893Y-10 Pin Descriptions The tables in this section list the ICS1893Y-10 pins by their functional grouping. 8.3.1 Transformer Interface Pins Table 8-2 lists the pins for the transformer interface group of pins. Table 8-2. Transformer Interface ...
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ICS1893Y-10 Data Sheet - Release 8.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins Table 8-3 lists the pins for the multi-function group of pins (that is, the multiplexed PHY Address / LED pins). Note: 1. During either a power-on ...
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ICS1893Y-10 - Release Table 8-3. PHY Address and LED Pins Pin Pin Pin Name Number Type P1CL 59 Input or Output P2LI 60 Input or Output ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description PHY ...
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ICS1893Y-10 Data Sheet - Release Table 8-3. PHY Address and LED Pins Pin Pin Pin Name Number Type P3TD 62 Input or Output P4RD 64 Input or Output ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893Y-10 - Release 8.3.3 Configuration Pins Table 8-4 lists the configuration pins. Table 8-4. Configuration Pins Pin Pin Name Number Type 10/100SEL 2 Input or Output 10TCSR 9 Input 100TCSR 10 Input ANSEL 26 Input or Output DPXSEL 24 Input ...
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ICS1893Y-10 Data Sheet - Release Table 8-4. Configuration Pins (Continued) Pin Pin Name Number Type HW/SW 23 Input LOCK 27 Output LSTA 21 Output MII/SI 19 Input NOD/REP 1 Input REF_IN 53 Input REF_OUT 52 Input RESETn 18 Input ICS1893Y-10 ...
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ICS1893Y-10 - Release 8.3.4 MAC/Repeater Interface Pins This section lists pin descriptions for each of the following interfaces • Section 8.3.4.1, “MAC/Repeater Interface Pins for Media Independent Interface” • Section 8.3.4.2, “MAC/Repeater Interface Pins for 100M Symbol Interface” • Section ...
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ICS1893Y-10 Data Sheet - Release Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type MDIO 30 Input/ Output RXCLK 38 Output ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893Y-10 - Release Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXD0, 35, Output RXD1, 34, RXD2, 33, RXD3 32 RXDV 36 Output RXER 39 Output RXTRI 41 Input TXCLK 43 Output ...
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ICS1893Y-10 Data Sheet - Release Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type TXEN 44 Input TXER 42 Input ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description ...
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ICS1893Y-10 - Release 8.3.4.2 MAC/Repeater Interface Pins for 100M Symbol Interface Table 8-6 lists the MAC/Repeater Interface pin descriptions for the 100M Symbol Interface. Table 8-6. MAC/Repeater Interface Pins: 100M Symbol Interface MII Pin 100M Pin Name Symbol No. Pin ...
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ICS1893Y-10 Data Sheet - Release Table 8-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXCLK SRCLK 38 ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Type Output ...
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ICS1893Y-10 - Release Table 8-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXD0, SRD0, 35, RXD1, SRD1, 34, RXD2, SRD2, 33, RXD3 SRD3 32 RXDV – 36 RXER SRD4 39 RXTRI ...
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ICS1893Y-10 Data Sheet - Release 8.3.4.3 MAC/Repeater Interface Pins for 10M Serial Interface Table 8-7 lists the MAC/Repeater Interface pin descriptions for the 10M Serial Interface. Table 8-7. MAC/Repeater Interface Pins: 10M Serial Interface MII Pin 100M Pin Name Symbol ...
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ICS1893Y-10 - Release Table 8-7. MAC/Repeater Interface Pins: 10M Serial Interface (Continued) MII Pin 100M Pin Name Symbol No. Pin Name RXDV 10RXDV 36 RXER – 39 RXTRI 41 TXCLK 10TCLK 43 TXD0 10TD 45 TXD1, – 46, TXD2, 47, ...
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ICS1893Y-10 Data Sheet - Release 8.3.5 Reserved Pins Table 8-8 lists the reserved pins. Table 8-8. Reserved Pins Pin Pin Pin Name Number Type REG 20 Input 8.3.6 Ground and Power Pins Table 8-9 lists the ground and power pins. ...
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ICS1893Y-10 - Release Chapter 9 DC and AC Operating Conditions 9.1 Absolute Maximum Ratings Table 9-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893Y-10. These ratings, which are standard values for ICS commercially rated parts, ...
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ICS1893Y-10 Data Sheet - Release 9.3 Recommended Component Values Table 9-3. Recommended Component Values for ICS1893Y-10 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std 802.3 requirements that drive the tolerance ...
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ICS1893Y-10 - Release 9.4 DC Operating Characteristics This section lists the ICS1893Y-10 DC operating characteristics. 9.4.1 DC Operating Characteristics for Supply Current Table 9-4 lists the DC operating characteristics for the supply current to the ICS1893Y-10 under various conditions. Note: ...
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ICS1893Y-10 Data Sheet - Release 9.4.3 DC Operating Characteristics for REF_IN Table 9-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 9-6. 3.3-V DC Operating Characteristics for REF_IN ...
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ICS1893Y-10 - Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The ...
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ICS1893Y-10 Data Sheet - Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time ...
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ICS1893Y-10 - Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for the time periods. Table ...
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ICS1893Y-10 Data Sheet - Release 9.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing. The time periods consist of timings of ...
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ICS1893Y-10 - Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • ...
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ICS1893Y-10 Data Sheet - Release 9.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on ...
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ICS1893Y-10 - Release 9.5.7 MII Management Interface Timing Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 9-14. MII Management Interface Timing Time ...
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ICS1893Y-10 Data Sheet - Release 9.5.8 10M Serial Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of timings of signals on the following pins: • TP_RX (the MDI ...
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ICS1893Y-10 - Release 9.5.9 10M Media Independent Interface: Receive Latency Table 9-16 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII ...
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ICS1893Y-10 Data Sheet - Release 9.5.10 10M Serial Interface: Transmit Latency Table 9-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the ...
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ICS1893Y-10 - Release 9.5.11 10M Media Independent Interface: Transmit Latency Table 9-18 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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ICS1893Y-10 Data Sheet - Release 9.5.12 MII / 100M Stream Interface: Transmit Latency Table 9-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following ...
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ICS1893Y-10 - Release 9.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-20 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN ...
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ICS1893Y-10 Data Sheet - Release 9.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-21 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893Y-10 - Release 9.5.15 100M MII / 100M Stream Interface: Receive Latency Table 9-22 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following ...
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ICS1893Y-10 Data Sheet - Release 9.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that ...
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ICS1893Y-10 - Release 9.5.17 Reset: Power-On Reset Table 9-24 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-18 shows the timing diagram ...
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ICS1893Y-10 Data Sheet - Release 9.5.18 Reset: Hardware Reset and Power-Down Table 9-25 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • ...
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ICS1893Y-10 - Release 9.5.19 10Base-T: Heartbeat Timing (SQE) Table 9-26 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • TXEN • ...
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ICS1893Y-10 Data Sheet - Release 9.5.20 10Base-T: Jabber Timing Table 9-27 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and ...
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ICS1893Y-10 - Release 9.5.21 10Base-T: Normal Link Pulse Timing Table 9-28 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-28. 10Base-T Normal Link Pulse Timing Time ...
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ICS1893Y-10 - Release 9.5.22 Auto-Negotiation Fast Link Pulse Timing Table 9-29 lists the significant time periods for the ICS1893Y-10 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure ...
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ICS1893Y-10 - Release Chapter 10 Physical Dimensions of ICS1893Y-10 Package This section gives the physical dimensions for the ICS1893Y-10 package. • The lead count ( leads. • The nominal footprint (that is the body) is 10.0 mm. Table ...
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ICS1893Y-10 Data Sheet - Release Figure 10-1. ICS1893Y-10 Physical Dimensions ICS1893Y-10 Rev F 1/20/04 Chapter 10 Physical Dimensions of ICS1893Y- Standoff Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. ...
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... ICS1893Y-10 - Release Chapter 11 Ordering Information Figure 11-1. ICS1893Y-10 Ordering Information Part / Order Number ICS1893Y-10 ICS1893YI-10 1893YI-10 ICS1893Y-10LF 1893Y-10LF ICS1893YI-10LF 1893YI-10LF ICS1893Y-10 Rev F 1/20/04 Marking Package 1893Y-10 10x10 TQFP (Thin Quad Flat Pack) 10x10 TQFP (Thin Quad Flat Pack) 10x10 TQFP Lead Free 10x10 TQFP Lead Free Copyright © ...
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Integrated Circuit Systems, Inc. Corporate Headquarters: Silicon Valley: Web Site: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device ...