S29GL512S10TFI010 Spansion Inc., S29GL512S10TFI010 Datasheet - Page 18

• Manufacturer Part Number: S29GL512S10TFI010
• Description: SPZS29GL512S10TFI010 IC 512M PAGE-MODE F
• Manufacturer: Spansion Inc.

Specifications of S29GL512S10TFI010

• Data Bus Width: 16 bit
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 100 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 60 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Compliant

3.
3.1
3.2
3.3
18
3.1.1
3.1.2
Data Protection
Device Protection Methods
Command Protection
Secure Silicon Region (OTP)
Power-Up Write Inhibit
Low V
The device offers several features to prevent malicious or accidental erasure of any sector via hardware
means.
RESET#, CE#, WE#, and, OE# are ignored during Power-On Reset (POR). During POR, the device can not
be selected, will not accept commands on the rising edge of WE#, and does not drive outputs. The Host
Interface Controller (HIC) and Embedded Algorithm Controller (EAC) are reset to their standby states, ready
for reading array data, during POR. CE#, WE#, and OE# must go to V
At the end of POR the device conditions are:
 all internal configuration information is loaded,
 the device is in read mode,
 the Status Register is at default value,
 all bits in the DYB ASO are set to un-protect all sectors,
 the Write Buffer is loaded with all 1’s,
 the EAC is in the standby state.
When V
during V
prevent unintentional writes when V
Embedded Algorithms are initiated by writing command sequences into the EAC command memory. The
command memory array is not readable by the host system and has no ASO. Each host interface write is a
command or part of a command sequence to the device. The EAC examines the address and data in each
write transfer to determine if the write is part of a legal command sequence. When a legal command
sequence is complete the EAC will initiate the appropriate EA.
Writing incorrect address or data values, or writing them in an improper sequence, will generally result in the
EAC returning to its Standby state. However, such an improper command sequence may place the device in
an unknown state, in which case the system must write the reset command, or possibly provide a hardware
reset by driving the RESET# signal Low, to return the EAC to its Standby state, ready for random read.
The address provided in each write may contain a bit pattern used to help identify the write as a command to
the device. The upper portion of the address may also select the sector address on which the command
operation is to be performed. The Sector Address (SA) includes
byte address signals a
(system byte address signals a11 through a1).
The data in each write may be: a bit pattern used to help identify the write as a command, a code that
identifies the command operation to be performed, or supply information needed to perform the operation.
See
The Secure Silicon Region (SSR) provides an extra flash memory area that can be programmed once and
permanently protected from further changes i. e. it is a One Time Program (OTP) area. The SSR is
1024 bytes in length. It consists of 512 bytes for Factory Locked Secure Silicon Region and 512 bytes for
Customer Locked Secure Silicon Region.
Table 6.1 on page 57
CC
CC
CC
is less than V
Write Inhibit
power-up and power-down. The system must provide the proper signals to the control pins to
max
D a t a
LKO
through a17). A command bit pattern is located in A10 to A0 flash address bits
for a listing of all commands accepted by the device.
, the HIC does not accept any write cycles and the EAC resets. This protects data
S h e e t
GL-S MirrorBit
CC
is greater than V
( A d v a n c e
®
Family
LKO
.
I n f o r m a t i o n )
A
S29GL_128S_01GS_00_01 February 11, 2011
MAX
through A16 flash address bits (system
IH
before the end of POR (t
VCS
).