S29GL512S10TFI010 Spansion Inc., S29GL512S10TFI010 Datasheet - Page 33

• Manufacturer Part Number: S29GL512S10TFI010
• Description: SPZS29GL512S10TFI010 IC 512M PAGE-MODE F
• Manufacturer: Spansion Inc.

Specifications of S29GL512S10TFI010

• Data Bus Width: 16 bit
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: CFI
• Access Time: 100 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 60 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Compliant

February 11, 2011 S29GL_128S_01GS_00_01
5.3.3
5.3.4
5.3.4.1
5.3.4.2
Blank Check
Erase Methods
Program operations can be interrupted as often as necessary but in order for a program operation to progress
to completion there must be some periods of time between resume and the next suspend command greater
than or equal to t
Program suspend and resume is not supported while entered in an ASO. While in program suspend entry into
ASO is not supported.
The Blank Check command will confirm if the selected main flash array sector is erased. The Blank Check
command does not allow for reads to the array during the Blank Check. Reads to the array while this
command is executing will return unknown data.
To initiate a Blank Check on a Sector, write 33h to address 555h in the Sector, while the EAC is in the
standby state
The Blank Check command may not be written while the device is actively programming or erasing or
suspended.
Use the Status Register read to confirm if the device is still busy and when complete if the sector is blank or
not. Bit 7 of the Status Register will show if the device is performing a Blank Check (similar to an erase
operation). Bit 5 of the Status Register will be cleared to 0 if the sector is erased and set to 1 if not erased.
As soon as any bit is found to not be erased, the device will halt the operation and report the results.
Once the Blank Check is completed, the EAC will return to the Standby State.
Chip Erase
The chip erase function erases the entire main Flash Memory Array. The device does not require the system
to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire
memory for an all 0 data pattern prior to electrical erase. After a successful chip erase, all locations within the
device contain FFFFh. The system is not required to provide any controls or timings during these operations.
The chip erase command sequence is initiated by writing two unlock cycles, followed by a set up command.
Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm.
When the Embedded Erase algorithm is complete, the EAC returns to the standby state. Note that while the
Embedded Erase operation is in progress, the system can not read data from the device. The system can
determine the status of the erase operation by reading the Status Register or using Data Polling. Refer to
Status Register on page 38
more information. Once the chip erase operation has begun, only a Status Read, Hardware RESET or Power
cycle are valid. All other commands are ignored. However, a Hardware Reset or Power Cycle immediately
terminates the erase operation and returns to read mode after t
terminated, the chip erase command sequence must be reinitiated once the device has returned to the idle
state to ensure data integrity.
See
Operations on page 86
Sectors protected by the ASP DYB and PPB lock bits will not be erased. See
protected during chip erase, chip erase will skip the protected sector and continue with next sector erase. The
status register erase status bit and sector lock bit are not set to 1 by a failed erase on a protected sector.
Sector Erase
The sector erase function erases one sector in the memory array. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire
sector for an all 0 data pattern prior to electrical erase. After a successful sector erase, all locations within the
erased sector contain FFFFh. The system is not required to provide any controls or timings during these
operations. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set
up command. Two additional unlock write cycles are then followed by the address of the sector to be erased,
and the sector erase command.
D a t a
Table 5.6 on page
S h e e t
PRS
in
47,
for parameters and timing diagrams.
Embedded Algorithm Controller (EAC) on page
( A d v a n c e
Asynchronous Write Operations on page 80
for information on these status bits. Refer to
GL-S MirrorBit
I n f o r m a t i o n )
®
Family
RPH
time. If a chip erase operation is
25.
and
Data Polling Status on page 40
Alternate CE# Controlled Write
ASP on page
19. If a sector is
for
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