EVAL-AD9837SDZ Analog Devices Inc, EVAL-AD9837SDZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-AD9837SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of EVAL-AD9837SDZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9837
• Primary Attributes: -
• Secondary Attributes: Graphical User Interface
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Generator
• Kit Contents: Software CD, USB Cable
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9837
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9837 has a standard 3-wire serial interface that is
compatible with the SPI, QSPI™, MICROWIRE®, and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the control
of a serial clock input, SCLK. The timing diagram for this oper-
ation is given in Figure 3.
FSYNC is a level triggered input that acts as a frame synchroni-
zation and chip enable input. Data can be transferred into the
device only when FSYNC is low. To start the serial data transfer,
FSYNC should be taken low, observing the minimum FSYNC
to SCLK falling edge setup time, t
goes low, serial data is shifted into the input shift register of the
device on the falling edges of SCLK for 16 clock pulses. FSYNC
can be taken high after the 16th falling edge of SCLK, observing
the minimum SCLK falling edge to FSYNC rising edge time, t
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
pulses and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded
while FSYNC is held low; FSYNC goes high only after the 16th
SCLK falling edge of the last word loaded.
The SCLK can be continuous, or it can idle high or low between
write operations. In either case, it must be high when FSYNC
goes low (t
For an example of how to program the AD9837, see the
Application Note
AD9837 has the same register settings as the AD9833/AD9834.
11
).
on the Analog Devices, Inc., website. The
SLEEP12
SLEEP1
RESET
MODE + OPBITEN
DIV2
OPBITEN
D15
0
D14
0
ACCUMULATOR
(28-BIT)
PHASE
7
D13
B28
(see Table 2). After FSYNC
HLB
D12
FSEL
D11
ROM
SIN
PSEL
D10
AN-1070
Figure 20. Function of Control Bits
D9
0
Rev. 0 | Page 13 of 28
0
MUX
1
8
.
RESET
D8
SLEEP1
DIVIDE
D7
BY 2
LATENCY PERIOD
A latency period is associated with each asynchronous write
operation in the AD9837. If a selected frequency or phase
register is loaded with a new word, there is a delay of seven
or eight MCLK cycles before the analog output changes. The
delay can be seven or eight cycles, depending on the position
of the MCLK rising edge when the data is loaded into the
destination register.
CONTROL REGISTER
The AD9837 contains a 16-bit control register that allows the
user to configure the operation of the AD9837. All control bits
other than the MODE bit are sampled on the internal falling
edge of MCLK.
Figure 20 illustrates the functions of the control bits. Table 7
describes the individual bits of the control register. The different
functions and the various output options of the AD9837 are
described in more detail in the following sections.
To inform the AD9837 that the contents of the control register
will be altered, Bit D15 and Bit D14 must be set to 0, as shown
in Table 6.
Table 6. Control Register Bits
D15
0
SLEEP12
D6
1
MUX
0
(LOW POWER)
10-BIT DAC
OPBITEN
D5
(ENABLE)
OUTPUT
DIGITAL
D14
0
D4
0
DIV2
D3
D2
0
MODE
D1
D13 to D0
Control bits
VOUT
D0
0
AD9837