EVAL-AD9837SDZ Analog Devices Inc, EVAL-AD9837SDZ Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD9837SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of EVAL-AD9837SDZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9837
• Primary Attributes: -
• Secondary Attributes: Graphical User Interface
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Generator
• Kit Contents: Software CD, USB Cable
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9837
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FREQUENCY AND PHASE REGISTERS
The AD9837 contains two frequency registers and two phase
registers, which are described in Table 8.
Table 8. Frequency and Phase Registers
Register
FREQ0
FREQ1
PHASE0
PHASE1
The analog output from the AD9837 is
where FREQREG is the value loaded into the selected frequency
register.
This signal is phase shifted by
where PHASEREG is the value contained in the selected phase
register.
The relationship of the selected output frequency and the refer-
ence clock frequency must be considered to avoid unwanted
output anomalies.
The flowchart in Figure 24 shows the routine for writing to the
frequency and phase registers of the AD9837.
Writing to a Frequency Register
When writing to a frequency register, Bit D15 and Bit D14 of
the control register give the address of the frequency register
(see Table 9).
Table 9. Frequency Register Bits
D15
0
1
To change the entire contents of a frequency register, two consec-
utive writes to the same address must be performed because the
frequency registers are 28 bits wide. The first write contains the
14 LSBs, and the second write contains the 14 MSBs. For this
mode of operation, the B28 control bit (Bit D13) must be set
to 1. An example of a 28-bit write is shown in Table 10.
f
2π/4096 × PHASEREG
MCLK
/2
28
12 bits
12 bits
Size
28 bits
28 bits
D14
1
0
× FREQREG
Description
Frequency Register 0.
When the FSEL bit = 0, the FREQ0
register defines the output frequency
as a fraction of the MCLK frequency.
Frequency Register 1.
When the FSEL bit = 1, the FREQ1
register defines the output frequency
as a fraction of the MCLK frequency.
Phase Offset Register 0.
When the PSEL bit = 0, the contents of
the PHASE0 register are added to the
output of the phase accumulator.
Phase Offset Register 1.
When the PSEL bit = 1, the contents of
the PHASE1 register are added to the
output of the phase accumulator.
D13 to D0
14 FREQ0 register bits
14 FREQ1 register bits
Rev. 0 | Page 15 of 28
Table 10. Writing 0xFFFC000 to the FREQ0 Register
SDATA Input
0010 0000 0000 0000
0100 0000 0000 0000
0111 1111 1111 1111
Note, however, that continuous writes to the same frequency
register may result in intermediate updates during the writes. If
a frequency sweep, or something similar, is required, it is recom-
mended that users alternate between the two frequency registers.
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered; with fine tuning, only the 14 LSBs are altered. By
setting the B28 control bit (Bit D13) to 0, the 28-bit frequency
register operates as two 14-bit registers, one containing the
14 MSBs and the other containing the 14 LSBs. In this way, the
14 MSBs of the frequency word can be altered independently
of the 14 LSBs, and vice versa. The HLB bit (Bit D12) in the
control register identifies which 14 bits are being altered (see
Table 11 and Table 12).
Table 11. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register
SDATA Input
0000 0000 0000 0000
1011 1111 1111 1111
Table 12. Writing 0x00FF to the 14 MSBs of the FREQ0 Register
SDATA Input
0001 0000 0000 0000
0100 0000 1111 1111
Writing to a Phase Register
When writing to a phase register, Bit D15 and Bit D14 are set to
11. Bit D13 identifies the phase register that is being loaded.
Table 13. Phase Register Bits
D15
1
1
D14
1
1
D13
0
1
Result of Input Word
Control word write
(D15, D14 = 00), B28 (D13) = 1,
HLB (D12) = X
FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x3FFF
Result of Input Word
Control word write
(D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 0, that is, LSBs
FREQ1 register write
(D15, D14 = 10), 14 LSBs = 0x3FFF
Result of Input Word
Control word write
(D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 1, that is, MSBs
FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x00FF
D12
X
X
D11 to D0
12 PHASE0 register bits
12 PHASE1 register bits
AD9837