EVAL-AD9837SDZ Analog Devices Inc, EVAL-AD9837SDZ Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD9837SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of EVAL-AD9837SDZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9837
• Primary Attributes: -
• Secondary Attributes: Graphical User Interface
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Generator
• Kit Contents: Software CD, USB Cable
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9837
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AD9837
Table 7. Control Register Bit Descriptions
Bit
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bit Name
B28
HLB
FSEL
PSEL
Reserved
RESET
SLEEP1
SLEEP12
OPBITEN
Reserved
DIV2
Reserved
MODE
Reserved
Description
Two write operations are required to load a complete word into either of the frequency registers.
B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write
contains the 14 LSBs of the frequency word, and the second write contains the 14 MSBs. The first two bits of each
16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both
consecutive writes. See Table 9 for the appropriate addresses. The write to the frequency register occurs after both
words have been loaded, so the register never holds an intermediate value. An example of a complete 28-bit write
is shown in Table 10. Note, however, that consecutive 28-bit writes to the same frequency register are not allowed;
to execute consecutive 28-bit writes, you must alternate between the frequency registers.
B28 = 0 configures the 28-bit frequency register to operate as two 14-bit registers, one containing the 14 MSBs and
the other containing the 14 LSBs. In this way, the 14 MSBs of the frequency word can be altered independently of
the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency
address. Bit D12 (HLB) informs the AD9837 whether the bits to be altered are the 14 MSBs or the 14 LSBs.
This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the
remaining 14 bits. This is useful if the complete 28-bit resolution is not required. The HLB bit is used in conjunction
with the B28 bit (Bit D13). The HLB bit indicates whether the 14 bits to be loaded are transferred to the 14 MSBs or
the 14 LSBs of the addressed frequency register. Bit D13 (B28) must be set to 0 to change the MSBs or LSBs of a
frequency word separately. When Bit D13 (B28) is set to 1, the HLB bit is ignored.
HLB = 1 allows a write to the 14 MSBs of the addressed frequency register.
HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator (see Table 8).
The PSEL bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the
phase accumulator (see Table 8).
This bit should be set to 0.
This bit controls the reset function.
RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale.
RESET = 0 disables the reset function (see the Reset Function section).
This bit enables or disables the internal MCLK.
SLEEP1 = 1 disables the internal MCLK. The DAC output remains at its present value because the NCO is no longer
accumulating.
SLEEP1 = 0 enables the internal MCLK (see the Sleep Function section).
This bit powers down the on-chip DAC.
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9837 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active (see the Sleep Function section).
This bit, in association with the MODE bit (Bit D1), controls the output at the VOUT pin (see Table 16).
OPBITEN = 1 causes the output of the DAC to no longer be available at the VOUT pin. Instead, the MSB (or MSB/2) of
the DAC data is connected to the VOUT pin. This output is useful as a coarse clock source. The DIV2 bit (Bit D3)
controls whether the VOUT pin outputs the MSB or the MSB/2.
OPBITEN = 0 connects the output of the DAC to VOUT. The MODE bit (Bit D1) determines whether the output is
sinusoidal or triangular.
This bit must be set to 0.
DIV2 is used in association with Bit D5 (OPBITEN). See Table 16.
DIV2 = 1 causes the MSB of the DAC data to be output at the VOUT pin.
DIV2 = 0 causes the MSB/2 of the DAC data to be output at the VOUT pin.
This bit must be set to 0.
This bit, in association with the OPBITEN bit (Bit D5), controls the output at the VOUT pin when the on-chip DAC is
connected to VOUT. This bit should be set to 0 if the OPBITEN bit is set to 1 (see Table 16).
MODE = 1 bypasses the SIN ROM, resulting in a triangle output from the DAC.
MODE = 0 uses the SIN ROM to convert the phase information into amplitude information, resulting in a sinusoidal
signal at the output. (The OPBITEN bit (Bit D5) must also be set to 0 for sinusoidal output.)
This bit must be set to 0.
Rev. 0 | Page 14 of 28