MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 237

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.1.2
This subsection lists and briefly describes all operating modes supported by the S12CPMU.
4.38.1.2.1
The voltage regulator is in Full Performance Mode (FPM).
The Phase-locked Loop (PLL) is on.
The Internal Reference Clock (IRC1M) is on.
The API is available.
4.38.1.2.2
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Power mode (RPM)
The API is available
The Phase Locked Loop (PLL) is off
The Internal Reference Clock (IRC1M) is off
Core Clock, Bus Clock and BDM Clock are stopped
Depending on the setting of the PSTP and the OSCE bit, Stop mode can be differentiated between Full Stop mode (PSTP = 0 or
OSCE=0) and Pseudo Stop mode (PSTP = 1 and OSCE=1).
Freescale Semiconductor
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PLL Engaged Internal (PEI)
— This is the default mode after System Reset and Power-on Reset.
— The Bus Clock is based on the PLLCLK.
— After reset the PLL is configured for 64 MHz VCOCLK operation
— The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
PLL Engaged External (PEE)
— The Bus Clock is based on the PLLCLK.
— This mode can be entered from default mode PEI by performing the following steps:
PLL Bypassed External (PBE)
— The Bus Clock is based on the Oscillator Clock (OSCCLK).
— This mode can be entered from default mode PEI by performing the following steps:
— The PLLCLK is still on to filter possible spikes of the external oscillator clock
Full Stop mode (pstp = 0 or osce=0)
The external oscillator (OSCLCP) is disabled
After wake-up from Full Stop mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). After wake-up
from Full Stop mode the COP and RTI are running on IRCCLK (COPOSCSEL=0, RTIOSCSEL=0)
Pseudo Stop Mode (PSTP = 1 and OSCE=1)
The external oscillator (OSCLCP) continues to run. If the respective enable bits are set the COP and RTI will continue
to run.
The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged
Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 16 MHz and Bus Clock is 8.0 MHz.
The PLL can be reconfigured for other bus frequencies.
– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary.
– Enable the external oscillator (OSCE bit)
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
Modes of Operation
Run Mode
Stop Mode
When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from
Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time
equivalent to the startup-time of the external oscillator t
mode.
MM912_634 Advance Information, Rev. 4.0
NOTE
UPOSC
before entering Pseudo Stop
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