MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 88

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.14.3.1.4
The CAEx bits select either center aligned outputs or left aligned output for both PWM channels. If the CAEx bit is set to a one,
the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left
aligned. See
description of the PWM output modes.
4.14.3.2
This register selects the prescale clock source for clocks A and B independently.
Note:
Freescale Semiconductor
Offset
83.
Reset
W
R
PCKB[2:0]
PCKA[2:0]
(83)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
6–4
2–0
0x61
Section 4.14.4.2.5, “Left Aligned Outputs”
PWM Prescale Clock Select Register (PWMPRCLK)
7
0
0
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channel 1. These three bits
determine the rate of clock B, as shown in
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channel 0. These three bits
determine the rate of clock A, as shown in
Register bits PCLK0 and PCLK1 can be written anytime. If a clock select changes while a
PWM signal is being generated, a truncated or stretched pulse can occur during the
transition.
PWM Center Align Enable (CAEx)
Write these bits only when the corresponding channel is disabled.
PCKB2
Table 121. PWM Prescale Clock Select Register (PWMPRCLK)
6
0
PCKB2
0
0
0
0
1
1
1
1
Table 122. PWMPRCLK - Register Field Descriptions
PCKB1
Table 123. Clock B Prescaler Selects
MM912_634 Advance Information, Rev. 4.0
5
0
PCKB1
0
0
1
1
0
0
1
1
and
Table
Table
PCKB0
Section 4.14.4.2.6, “Center Aligned Outputs”
NOTE
NOTE
4
0
123.
124.
PCKB0
0
1
0
1
0
1
0
1
Description
3
0
0
Value of Clock B
D2D clock / 128
D2D clock / 16
D2D clock / 32
D2D clock / 64
D2D clock / 2
D2D clock / 4
D2D clock / 8
D2D clock
PCKA2
2
0
PWM Control Module (PWM8B2C)
PCKA1
for a more detailed
1
0
Access: User read/write
PCKA0
0
0
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