STM32W108HBU64TR STMicroelectronics, STM32W108HBU64TR Datasheet - Page 122

• Manufacturer Part Number: STM32W108HBU64TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU64TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General-purpose timers
10.1.8
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The OCyREF signal can be forced low by writing the TIM_OCyM bits to 100 in the
TIMx_CCMR1 register.
The comparison between the TIMx_CCRy shadow register and the counter is still performed
and allows the INT_TIMxCCRyIF flag to be set. Interrupt requests can be sent accordingly.
This is described in
Output compare mode
This mode is used to control an output waveform or to indicate when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
●
●
●
The TIMx_CCRy registers can be programmed with or without buffer registers using the
TIM_OCyBE bit in the TIMx_CCMR1 register.
In output compare mode, the update event has no effect on OCyREF or the OCy output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in one pulse mode).
Procedure:
1.
2.
3.
4.
5.
To control the output waveform, software can update the TIMx_CCRy register at any time,
provided that the buffer register is not enabled (TIM_OCyBE = 0). Otherwise TIMx_CCRy
shadow register is updated only at the next update event. An example is given in
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (the TIM_OCyM bits in the TIMx_CCMR1 register) and the output
polarity (the TIM_CCyP bit in the TIMx_CCER register). The output can remain
unchanged (TIM_OCyM = 000), be set active (TIM_OCyM = 001), be set inactive
(TIM_OCyM = 010), or can toggle (TIM_OCyM = 011) on the match.
Sets a flag in the interrupt flag register (the INT_TIMCCyIF bit in the INT_TIMxFLAG
register).
Generates an interrupt if the corresponding interrupt mask is set (the TIM_CCyIF bit in
the INT_TIMxCFG register).
Select the counter clock (internal, external, and prescaler).
Write the desired data in the TIMx_ARR and TIMx_CCRy registers.
Set the INT_TIMCCyIF bit in INT_TIMxCFG if an interrupt request is to be generated.
Select the output mode. For example, you must write TIM_OCyM = 011, TIM_OCyBE =
0, TIM_CCyP = 0 and TIM_CCyE = 1 to toggle the OCy output pin when TIMx_CNT
matches TIMx_CCRy, TIMx_CCRy buffer is not used, OCy is enabled and active high.
Enable the counter by setting the TIM_CEN bit in the TIMx_CR1 register.
Section 10.1.8: Output compare mode on page
Doc ID 16252 Rev 8
STM32W108CB, STM32W108HB
122.
Figure
34.