MCIMX537CVV8C Freescale Semiconductor, MCIMX537CVV8C Datasheet - Page 201

• Manufacturer Part Number: MCIMX537CVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX537CVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7
Table 121
Freescale Semiconductor
Number
Rev 3
Rev 2
Rev.
Revision History
06/2011 • In
05/2011 • In
provides a revision history for this data sheet.
Date
• In
• Updated the note on
• Added 167 MHz ARM specification to
• Modified VDD_FUSE design best practice footnote on
• Changed VDD_FUSE max current to 120 mA in
• Deleted the last row of
• Added
• Made changes related to text, tables, and figures in
• Removed the Standard Serial Interfaces section.
• In
• In
• In
• In
• Updated keeper values in
• Fixed titles of
• Updated
• Added
• Added
• Deleted the second footnote of
• Deleted the Revision 1.0 EIM Internal Module Multiplexing table.
• Deleted the CKIL Electrical Specifications table.
• Deleted the CSPI Slave Mode Timing Parameters table .
• Updated the last paragragh of
• Changed the title of the
• Added
• Updated
• Removed the “Differential pulse skew” row from
• Updated
• Updated
• Updated
• Updated the second footnote on
and third column headings.
added a row for MCIMX538DZK1C and updated the PCIMX538DZK1C row.
page
(DDR2/LVDDR2, LPDDR2, and
ACCZ test results, and changing note about DDR load model.
pull-up/down from 250/120 nA to 2 μA, all input currents with pull-up from 0.12 μΑ to 2 μA when Vin =
OVDD, and input current with pull-down from 0.25 μA to 2 μA when Vin = 0.
pull-up/down from 250/120 nA to 1 μA, all input currents with pull-up from 0.12 μΑ to 1 μA when Vin =
OVDD, and input current with pull-down from 0.25 μA to 1 μA when Vin = 0.
pull-up/down from 300/63 nA to 1 μA, all input currents with pull-up from 0.06 μΑ to 1 μA when Vin =
OVDD, and input current with pull-down from 0.3 μA to 1 μA when Vin = 0.
Output Buffer Impedance.”
on page 45
on page
Section 4.1.1, “Absolute Maximum
Table 116, "Additional PCB connections for PoP NAND Flash," on page
Table 1, "Ordering Information," on page
Table 11, "GPIO I/O DC Electrical Characteristics," on page
Table
Table 15, "LVIO DC Electrical Characteristics," on page
Table 16, "UHVIO DC Electrical Characteristics," on page
Table 121. i.MX53xD Data Sheet Document Revision History
i.MX53xD Applications Processors for Consumer Products, Rev. 3
20.
Section 4.1.2.2, “PoP Package Thermal Resistance,”
Figure 27, "DTACK Write Access (DAP=0)," on page
Table 19, "DDR Output Driver Average Impedance," on page
Section 6.3.2.2, “PoP Memory Support and Signal Cross
12,
154.
Table 65, "Asynchronous Parallel Interface Timing Parameters (Access Level)," on page
Figure 2, "Power Up Detailed Sequence," on page
Table 36, " NFC—Timing Characteristics," on page
Table 64, "Asynchronous Display Interface Timing Parameters (Pixel Level)," on page
Table 101, "USB Timing Specification for Normal ULPI Mode," on page
.
Table
Figure 18
13, and
page 6
Table 10, "USB Interface Current Consumption," on page
Section 4.4.2, “DDR Output Driver Average
through
Table 11
Table
in
Section 4.7.8.6.1, “IPU Display Operating Signals.”
Section 1.2,
Table 33, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page
DDR3). Changes include adding LPDDR2 waves, updating timings by
14, changed input current from the nA range to 1 μA.
Figure
Table 112, "19 x 19 mm Signal Assignments, Power Rails, and I/O,"
through
Substantive Change(s)
Ratings,” updated the caution note on page 17.
Table 7, "i.MX53xD Operating Ranges," on page
26, to fit original EIM AC spec.
3, deleted the row for part number PCIMX535DVV1B,
“Features.”
Table
Table 30, "AC Electrical Characteristics of LVDS Pad,"
Table 9, "Maximal Supply Currents," on page
16.
Section 4.6.7, “DDR SDRAM Specific Parameters
Table 7, "i.MX53xD Operating Ranges," on
33, changed input current with no
27.
62.
according to package design report.
34, changed input current with no
52.
29, changed input current with no
Reference.”
Impedance,” from “LPDDR2 I/O
38.
178, updated the second
144.
25.
Revision History
20.
23.
105.
106.
47.
201