ISP1301BS ST-Ericsson Inc, ISP1301BS Datasheet - Page 24

• Manufacturer Part Number: ISP1301BS
• Description: IC USB OTG TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1301BS

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 2.7 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1166; ISP1301BS,157

Philips Semiconductors
Table 31:
ISP1301_3
Product data sheet
Bit
Symbol
Reset
Access
Interrupt Enable High register: bit allocation
CR_INT
10.2 Interrupts
10.3 Auto-connect
R/S/C
7
0
Table 32:
Table 26
Table 26
an interrupt has been generated, the OTG Controller should be able to read the status of
each signal and the bit that indicates whether that signal generated the interrupt.
A bit in the Interrupt Latch register is set when any of these occurs:
The Interrupt Latch register bit is cleared by writing logic 1 to its clear address.
The Host Negotiation Protocol (HNP) in the OTG supplement specifies the following
sequence of events to transfer the role of the host from the A-device to the B-device:
The OTG supplement specifies that the time between the B-device de-asserting its DP
pull-up and the A-device asserting its pull-up must be less than 3 ms. For an A-device with
a slow interrupt response time, 3 ms may not be enough time to write an I
Bit
7
6
5
4
3
2
1
0
1. The A-device puts the bus in the suspend state.
2. The B-device simulates a disconnect by de-asserting its DP pull-up.
3. The A-device detects SE0 on the bus, and asserts its DP pull-up.
4. The B-device detects that the DP line is HIGH, and takes the role of the host.
•
•
•
The corresponding bit in the Interrupt Enable High register is set, and the associated
signal changes from LOW to HIGH.
The corresponding bit in the Interrupt Enable Low register is set, and the associated
signal changes from HIGH to LOW.
Writing logic 1 to its set address causes the corresponding bit to be set.
BDIS_
ACON
R/S/C
Symbol
CR_INT
BDIS_ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD
VBUS_VLD
6
0
indicates the signals that can generate interrupts. Any of the signals given in
can generate an interrupt when the signal becomes either LOW or HIGH. After
Interrupt Enable High register: bit description
ID_FLOAT
R/S/C
5
0
Rev. 03 — 21 February 2006
Description
interrupt enable for CR_INT status change from 0 to 1
interrupt enable for BDIS_ACON status change from 0 to 1
interrupt enable for ID_FLOAT status change from 0 to 1
interrupt enable for DM_HI status change from 0 to 1
interrupt enable for ID_GND status change from 0 to 1
interrupt enable for DP_HI status change from 0 to 1
interrupt enable for SESS_VLD status change from 0 to 1
interrupt enable for VBUS_VLD status change from 0 to 1
DM_HI
R/S/C
4
0
ID_GND
R/S/C
3
0
DP_HI
R/S/C
2
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SESS_VLD VBUS_VLD
USB OTG transceiver
R/S/C
1
0
ISP1301
2
C-bus
R/S/C
0
0
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