ISP1301BS ST-Ericsson Inc, ISP1301BS Datasheet - Page 26

• Manufacturer Part Number: ISP1301BS
• Description: IC USB OTG TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1301BS

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 2.7 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1166; ISP1301BS,157

Philips Semiconductors
11. Clock wake-up scheme
ISP1301_3
Product data sheet
11.1 Power-down event
11.2 Clock wake-up events
The following subsections explain the ISP1301 clock stop timing, events triggering the
clock to wake up, and the timing of the clock wake-up.
The clock is stopped when the GLOBAL_PWR_DN bit is set. It takes approximately 8 ms
for the clock to stop from the time the power-down condition is detected. The clock always
stops at its falling edge. The waveform is given in
The clock wakes up when any of the following events occur on the ISP1301 pins:
The event triggers the clock to start and a stable clock is guaranteed after about six clock
periods, which is approximately 8 s. The startup analog clock time is 10 s. Therefore,
the total estimated start time after a triggered event is about 20 s. The clock will always
start at its rising edge.
Waveforms of the clock wake-up because of different events are given in
Figure
Fig 7. Clock stopped using the GLOBAL_PWR_DN bit
Fig 8. Clock wake-up using SCL
•
•
•
•
•
•
GLOBAL_PWR_DN
SCL goes LOW.
V
SESS_VLD bit in the Interrupt Enable High register is set.
ID changes when mini-A plug is inserted, provided the ID_FLOAT bit in the Interrupt
Enable Low register is set.
ID changes when mini-A plug is removed, provided the ID_FLOAT bit in the Interrupt
Enable High register is set.
DP goes HIGH, provided the DP_HI bit in the Interrupt Enable High register is set.
DM goes HIGH, provided the DM_HI bit in the Interrupt Enable High register is set.
BUS
9,
Figure
goes above the session valid threshold (0.8 V to 2.0 V), provided the
CLOCK
SCL
10,
CLOCK
Figure 11
SCL
Rev. 03 — 21 February 2006
and
Figure
12.
20 s
Figure
8 ms
7.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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USB OTG transceiver
ISP1301
Figure
8,
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