MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 353

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

11.3.2.30 PMF Enable Control C Register (PMFENCC)
Read anytime and write only if MTG is set.
Freescale Semiconductor
Module Base + 0x0030
PWMRIEC
PWMENC
LDOKC
Reset
Field
7
1
0
W
R
PWMENC
PWM Generator C Enable — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit when set enables the PWM generator C and the PWM4 and PWM5 pins. When PWMENC
is clear, PWM generator C is disabled, and the PWM4 and PWM5 pins are in their inactive states unless the
OUTCTL4 and OUTCTL5 bits are set.
0 PWM generator C and PWM4–5 pins disabled unless the respective OUTCTL bit is set.
1 PWM generator C and PWM4–5 pins enabled.
Load Okay C — If MTG is clear, this bit reads zero and can not be written.
If MTG is set, this bit loads the PRSCC bits, the PMFMODC register and the PWMVAL4–5 registers into a set of
buffers. The buffered prescaler divisor C, PWM counter modulus C value, PWM4–5 pulse widths take effect at
the next PWM reload.
Set LDOKC by reading it when it is logic zero and then writing a logic one to it. LDOKC is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKC.
0 Do not load new modulus C, prescaler C, and PWM4–5 values.
1 Load prescaler C, modulus C, and PWM4–5 values.
Note: Do not set PWMENC bit before setting the LDOKC bit and do not clear the LDOKC bit at the same time
PWM Reload Interrupt Enable C — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit enables the PWMRFC flag to generate CPU interrupt requests.
0 PWMRFC CPU interrupt requests disabled
1 PWMRFC CPU interrupt requests enabled
0
7
as setting the PWMENC bit.
= Unimplemented or Reserved
Figure 11-36. PMF Enable Control C Register (PMFENCC)
0
0
6
Table 11-39. PMFENCC Field Descriptions
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
0
0
4
Description
0
0
3
0
0
2
LDOKC
0
1
PWMRIEC
0
0
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