MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 489

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Freescale Semiconductor
BKBMB[H:L]
RWBEN
RWAEN
Field
RWA
RWB
5:4
3
2
1
0
1
If PPAGE is selected.
BKAMBH:BKAMBL
Breakpoint Mask High Byte and Low Byte of Data (Second Address) — In dual mode, these bits may be
used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The
functionality is as given in
The x:0 case is for a full address compare. When a program page is selected, the full address compare will be
based on bits for a 20-bit compare. The registers used for the compare are {DBGCBX[5:0], DBGCBH[5:0],
DBGCBL[7:0]} where DBGCBX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU
address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit
compare. The registers used for the compare are {DBGCBH[7:0], DBGCBL[7:0]} which corresponds to CPU
address [15:0].
Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several
The 1:0 case is not sensible because it would ignore the high order address and compare the low order and
expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKBMBH
control bit).
The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes
sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCBX compares.
In full mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data
breakpoint. The functionality is as given in
Read/Write Comparator A Enable Bit — The RWAEN bit controls whether read or write comparison is enabled
for comparator A. See
for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator A Value Bit — The RWA bit controls whether read or write is used in compare for
comparator A. The RWA bit is not used if RWAEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Read/Write Comparator B Enable Bit — The RWBEN bit controls whether read or write comparison is enabled
for comparator B. See
for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Read/Write Comparator B Value Bit — The RWB bit controls whether read or write is used in compare for
comparator B. The RWB bit is not used if RWBEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Note: RWB and RWBEN are not used in full mode.
x:0
0:1
1:1
physical addresses may match with a single logical address. This problem may be avoided by using DBG
mode to generate breakpoints.
Table 16-16. Breakpoint Mask Bits for First Address
Table 16-15. DBGC3 Field Descriptions (continued)
Section 16.4.2.1.1, “Read or Write
Section 16.4.2.1.1, “Read or Write
Table
16K byte address range
256 byte address range
MC9S12E128 Data Sheet, Rev. 1.07
Full address compare
Address Compare
16-17.
Table
16-18.
Description
Comparison,” for more information. This bit is not useful
Comparison,” for more information. This bit is not useful
DBGCAX
Yes
Yes
Yes
1
1
1
DBGCAH
Chapter 16 Debug Module (DBGV1)
Yes
Yes
No
DBGCAL
Yes
No
No
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