ST72C334N2T6 STMicroelectronics, ST72C334N2T6 Datasheet - Page 38

• Manufacturer Part Number: ST72C334N2T6
• Description: Microcontrollers (MCU) Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334N2T6

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: In Transition

ST72334J/N, ST72314J/N, ST72124J
5.2 POWER SAVING MODES
5.2.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
Figure 27. Power saving mode consumption / transitions
5.2.2 HALT Modes
The HALT modes are the lowest power consump-
tion modes of the MCU. They are entered by exe-
cuting the ST7 HALT instruction (see Figure 29).
Two different HALT modes can be distinguished:
– HALT: main oscillator is turned off,
– ACTIVE-HALT: only main oscillator is running.
The decision to enter either in HALT or ACTIVE-
HALT mode is given by the main oscillator enable
interrupt flag (OIE bit in CROSS-MCCSR register:
see Table 7).
When entering HALT modes, the I bit in the CC
register is forced to 0 to enable interrupts.
The MCU can exit HALT or ACTIVE-HALT modes
on reception of an interrupt with Exit from Halt
Figure 28. HALT /ACTIVE-HALT Modes timing overview
38/125
Low
POWER CONSUMPTION
RUN
HALT
INSTRUCTION
HALT
ACTIVE-HALT
HALT OR ACTIVE-HALT
SLOW WAIT
INTERRUPT
RESET
OR
4096 CPU CYCLE
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
Mode capability or a reset (see Table 6 page 37).
A 4096 CPU clock cycles delay is performed be-
fore the CPU operation resumes (see Figure 28).
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up.
Table 7. HALT Modes selection
MCCSR
flag
OIE
0
1
WAIT
DELAY
HALT (reset if watchdog enabled)
ACTIVE-HALT (no reset if watchdog enabled)
Power Saving Mode entered when HALT
VECTOR
FETCH
instruction is executed
SLOW
RUN
RUN
CPU
).
High