MF5CWM National Semiconductor, MF5CWM Datasheet - Page 3

• Manufacturer Part Number: MF5CWM
• Description: IC FILTER MONO SW CAP SO14
• Manufacturer: National Semiconductor

Specifications of MF5CWM

• Filter Type: Universal Switched Capacitor
• Frequency - Cutoff Or Center: 30kHz
• Number Of Filters: 1
• Max-order: 2nd
• Voltage - Supply: 8 V ~ 14 V
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *MF5CWM

Output
Swing (Min)
Dynamic Range
(Note 4)
Maximum Output Short Circuit
Current (Note 5)
Filter Electrical Characteristics
limits apply over temperature T
OP-AMP Electrical Characteristics
face limits apply over temperature T
Logic Input Characteristics
All other limits T
Note 1 The typical junction-to-ambient thermal resistance (
Note 2 The accuracy of the Q value is a function of the center frequency (f
Characteristics’’
Note 3 V
Note 4 For
the MF5 with a 50 1 CLK ratio and 280 V rms for the MF5 with a 100 1 CLK ratio
Note 5 The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply These are the worst case conditions
Note 6 Typicals are at 25 C and represent most likely parametric norm
Note 7 Guaranteed and 100% tested
Note 8 Guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels
CMOS Clock
Input
TTL Clock
Input
Gain Bandwidth Product
Output Voltage Swing (Min)
Slew Rate
DC Open-Loop Gain
Input Offset Voltage (Max)
Input Bias Current
Maximum Output
Short Circuit
Current (Note 5)
os1
g
V
5V supplies the dynamic range is referenced to 2 82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 V rms for
os2
Parameter
Parameter
and V
A
Parameter
e
Min Logical ‘‘1’’
Input Voltage
Max Logical ‘‘0’’
Input Voltage
Min Logical ‘‘1’’
Input Voltage
Max Logical ‘‘0’’
Input Voltage
Min Logical ‘‘1’’
Input Voltage
Max Logical ‘‘0’’
Input Voltage
os3
BP LP pins
N AP HP pin
25 C
refer to the internal offsets as discussed in the Application Information section 3 4
Source
Sink
MIN s
Source
Sink
MIN s
T
A s
V
V
V
V
V
V
RL
a
L Sh
a
L Sh
a
L Sh
Conditions
T
Boldface limits apply over temperature T
T
e a
e a
e a
A s
e
MAX
JA
e
e a
e
Conditions
) of the 14 pin N package is 160 C W and 82 C W for the M package
3 5 k
RL
RL
V
(50 1 CLK ratio)
V
(100 1 CLK ratio)
0V
T
V
5V V
10V V
5V V
0V
pin9
pin9
MAX
For all other limits T
a
e
e
5V
e a
e b
e
Conditions
5 k
3 5 k
V
b
b
For all other limits T
b
a
5V
e b
e b
5V
5V
e
e a
g
3
0V
o
0 5% V
5V
5V
) This is illustrated in the curves under the heading ‘‘Typical Performance
(Note 6)
5V
Typical
g
g
2 5
7 0
3 0
80
10
20
g
4 2
5 0
0 5% V
b
A
e b
e
(Note 6)
Typical
25 C (Continued)
A
(Note 6)
Typical
5V
b
e
g
g
3 0
83
80
20
e b
g
25 C
4 0
4 2
(Note 7)
Tested
0 5% unless otherwise noted Boldface
Limit
g
g
5V
3 8
20
MIN s
(Note 7)
Tested
g
Limit
b
0 5% unless other noted Bold-
3 0
8 0
2 0
2 0
0 8
(Note 7)
Tested
3 0
Limit
g
g
T
3 8
3 8
A s
(Note 8)
Design
T
Limit
MAX
(Note 8)
Design
Limit
(Note 8)
Design
Limit
Units
V
MHz
mV
mA
mA
Units
pA
db
Units
V
mA
mA
dB
dB
V
V
V
V
V
V
V
V
s