IC I/O EXPANDER I2C 8B 16HVQFN

 

PCA9554BS,118

Manufacturer Part NumberPCA9554BS,118
DescriptionIC I/O EXPANDER I2C 8B 16HVQFN
ManufacturerNXP Semiconductors
PCA9554BS,118 datasheets

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Specifications of PCA9554BS,118

Package / Case16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFNInterfaceI²C, SMBus
Number Of I /o8Interrupt OutputYes
Frequency - Clock400kHzVoltage - Supply2.3 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
IncludesPORMounting StyleSMD/SMT
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithOM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
Other names568-3397-2
935271979118
PCA9554BS-T		  
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PCA9554/PCA9554A
8-bit I
Rev. 07 — 13 November 2006
1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I
were developed to enhance the NXP Semiconductors family of I
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in Application Note AN469 .
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
devices to share the same I
except that the fixed I
(eight of each) on the same I
2. Features
I
Operating power supply voltage range of 2.3 V to 5.5 V
I
5 V tolerant I/Os
I
Polarity Inversion register
I
Active LOW interrupt output
I
Low standby current
I
Noise filter on SCL/SDA inputs
I
No glitch on power-up
I
Internal power-on reset
I
8 I/O pins which default to 8 inputs
I
0 Hz to 400 kHz clock frequency
2
C-bus and SMBus I/O port with interrupt
2
C-bus/SMBus. The PCA9554A is identical to the PCA9554
2
C-bus address is different allowing up to sixteen of these devices
2
C-bus/SMBus.
Product data sheet
2
C-bus/SMBus applications and
2
C-bus I/O expanders.
2
C-bus address
2
C-bus address and allow up to eight

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PCA9554BS,118 Summary of contents

  • Page 1

    ... The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I were developed to enhance the NXP Semiconductors family of I The improvements include higher drive capability I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc ...

  • Page 2

    ... NXP Semiconductors I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16, HVQFN16 (2 versions Ordering information Table 1. Ordering information +85 C ...

  • Page 3

    ... NXP Semiconductors 4. Block diagram SCL SDA Fig 1. Block diagram of PCA9554/PCA9554A PCA9554_9554A_7 Product data sheet PCA9554/PCA9554A INPUT 2 I C-BUS/SMBus FILTER POWER-ON RESET All I/Os are set to inputs at reset. Rev. 07 — 13 November 2006 PCA9554/PCA9554A 2 8-bit I C-bus and SMBus I/O port with interrupt 8-bit ...

  • Page 4

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for DIP16 IO0 IO1 IO2 IO3 V SS Fig 4. Pin configuration for SSOP16 PCA9554_9554A_7 Product data sheet 8-bit I PCA9554N PCA9554AN SDA SCL 4 13 IO0 INT IO1 5 12 IO7 IO2 6 11 IO6 ...

  • Page 5

    ... NXP Semiconductors Fig 6. Pin configuration for SSOP20 terminal 1 index area Fig 7. Pin configuration for HVQFN16 PCA9554_9554A_7 Product data sheet INT 1 SCL 2 3 n.c. 4 SDA n. IO0 PCA9554BS PCA9554ABS SCL IO0 2 11 INT IO1 3 10 IO7 IO2 4 9 IO6 002aac490 Transparent top view (SOT629-1) Rev. 07 — ...

  • Page 6

    ... NXP Semiconductors 5.2 Pin description Table 2. Symbol IO0 IO1 IO2 IO3 V SS IO4 IO5 IO6 IO7 INT SCL SDA V DD n.c. [1] HVQFN package die supply ground is connected to both V connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level ...

  • Page 7

    ... NXP Semiconductors 6.1.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no external signal externally applied because of the internal pull-up resistors ...

  • Page 8

    ... NXP Semiconductors 6.1.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. ...

  • Page 9

    ... NXP Semiconductors 6.3 Interrupt output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from and output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register ...

  • Page 10

    ... NXP Semiconductors 6.5 Device address Fig 10. PCA9554 device address 6.6 Bus transactions Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown in Figure 12 the Read mode as shown in auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent ...

  • Page 11

    ... NXP Semiconductors slave address SDA START condition acknowledge from slave slave address (cont (repeated) START condition Fig 14. Read from register SCL slave address SDA START condition read from port data into port t v(INT_N) INT This figure assumes the command byte has previously been programmed with 00h. ...

  • Page 12

    ... NXP Semiconductors 7. Application design-in information MASTER CONTROLLER SCL SDA INT V SS Device address configured as 0100 100X for this example. IO0, IO1, IO2 configured as outputs. IO3, IO4, IO5 configured as inputs. IO6 and IO7 are not used and must be configured as outputs. ...

  • Page 13

    ... NXP Semiconductors 9. Static characteristics Table 9. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...

  • Page 14

    ... NXP Semiconductors Table 9. Static characteristics Symbol Parameter Select inputs A0, A1 LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI [1] V must be lowered to 0 order to reset part. DD [2] Each I/O must be externally limited to a maximum and the device must be limited to a maximum current of 100 mA. ...

  • Page 15

    ... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 17. Definition of timing PCA9554_9554A_7 Product data sheet 8-bit HD;DAT HIGH SU;DAT Rev. 07 — 13 November 2006 PCA9554/PCA9554A 2 C-bus and SMBus I/O port with interrupt t t HD;STA SU;STA SU;STO Sr © NXP B.V. 2006. All rights reserved. ...

  • Page 16

    ... NXP Semiconductors 11. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil); long body pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.7 0.51 3.7 inches 0.19 0.02 0.15 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 17

    ... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 18

    ... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 20. Package outline SOT338-1 (SSOP16) ...

  • Page 19

    ... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.4 mm 1.5 0.25 0 1.2 Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION IEC SOT266-1 Fig 21. Package outline SOT266-1 (SSOP20) ...

  • Page 20

    ... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 21

    ... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 22

    ... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 23

    ... NXP Semiconductors 12. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 13. Soldering 13.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fi ...

  • Page 24

    ... NXP Semiconductors packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 Table 11. Package thickness (mm) < 2.5 2.5 Table 12. Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during refl ...

  • Page 25

    ... NXP Semiconductors 13.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. ...

  • Page 26

    ... NXP Semiconductors Table 13. Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Package Surface mount BGA, HTSSON..T LFBGA, SQFP, SSOP..T VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] PLCC LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN ...

  • Page 27

    ... NXP Semiconductors 14. Abbreviations Table 14. Acronym ACPI CDM CMOS ESD FET GPIO HBM 2 I C-bus I/O LED MM PCB POR SMBus PCA9554_9554A_7 Product data sheet 8-bit I Abbreviations Description Advanced Configuration and Power Interface Charged Device Model Complementary Metal Oxide Semiconductor ElectroStatic Discharge ...

  • Page 28

    ... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added HVQFN16 (SOT758-1) and bare die package offerings • ...

  • Page 29

    ... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

  • Page 30

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Registers 6.1.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.2 Register 0 - Input Port register . . . . . . . . . . . . . 7 6.1.3 Register 1 - Output Port register 6.1.4 Register 2 - Polarity Inversion register . . . . . . . 8 6.1.5 Register 3 - Confi ...

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