PCA9555PW,112 NXP Semiconductors, PCA9555PW,112 Datasheet - Page 9

• Manufacturer Part Number: PCA9555PW,112
• Description: IC I/O EXPANDER I2C 16B 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9555PW,112

• Package / Case: 24-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA
• Number Of Lines (input / Output): 16 / 16
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 2.3 V to 5.5 V
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 16
• Number Of Output Lines: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3986-5; 935269569112; PCA9555PW; PCA9555PW

NXP Semiconductors
PCA9555_8
Product data sheet
6.5.1 Writing to the port registers
6.5 Bus transactions
Data is transmitted to the PCA9555 by sending the device address and setting the least
significant bit to a logic 0 (see
sent after the address and determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs.
The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration
Ports. After sending data to one register, the next data byte will be sent to the other
register in the pair (see
Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, each 8-bit register may be updated independently of the other registers.
Fig 9.
configuration
write polarity
shift register
shift register
shift register
write pulse
read pulse
data from
data from
data from
pulse
pulse
write
At power-on reset, all registers return to default values.
Simplified schematic of I/Os
configuration
register
D
CK
FF
Q
Q
Rev. 08 — 22 October 2009
Figure 10
Figure 8 “PCA9555 device
output port
register
D
CK
FF
and
Q
16-bit I
Figure
input port
register
polarity inversion
register
D
CK
D
CK
2
11). For example, if the first byte is sent to
C-bus and SMBus I/O port with interrupt
FF
FF
Q
Q
address”). The command byte is
Q1
Q2
100 k
PCA9555
© NXP B.V. 2009. All rights reserved.
output port
register data
V
I/O pin
V
input port
register data
to INT
polarity
inversion
register data
DD
SS
002aac703
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