PCA9501D,112 NXP Semiconductors, PCA9501D,112 Datasheet
PCA9501D,112
Specifications of PCA9501D,112
935272364112
PCA9501D
Related parts for PCA9501D,112
PCA9501D,112 Summary of contents
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PCA9501 8-bit I EEPROM and 6 address pins Rev. 04 — 10 February 2009 1. General description The PCA9501 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. The I/O expandable eight quasi-bidirectional data pins can be independently assigned ...
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... NXP Semiconductors I Low standby current I Operating power supply voltage range tolerant inputs/outputs 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ...
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... NXP Semiconductors 5. Block diagram SCL SDA Fig 1. 6. Pinning information 6.1 Pinning IO0 IO1 IO2 IO3 INT V Fig 2. PCA9501_4 Product data sheet 2 8-bit I C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM PCA9501 300 k INPUT FILTER POWER-ON RESET Block diagram of PCA9501 ...
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... NXP Semiconductors Fig 4. 6.2 Pin description Table 3. Symbol IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 INT SCL SDA V DD [1] HVQFN20 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
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... NXP Semiconductors 7. Functional description Refer also to data from shift register data to shift register Fig 5. 7.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in are incorporated on the hardware-selectable address pins. ...
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... NXP Semiconductors 7.2 Control register The PCA9501 contains a single 8-bit register called the Control register, which can be written and read via the I of the slave address. It contains the I/O operation information. 7.3 I/O operations (Refer also to Each of the PCA9501's eight I/Os can be independently used as an input or output. ...
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... NXP Semiconductors 7.3.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to V heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL ...
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... NXP Semiconductors MICROCONTROLLER Fig 10. Application of multiple PCA9501s with interrupt data into IO5 Fig 11. Interrupt generated by a change of input to IO5 7.4 Memory operations 7.4.1 Write operations Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long providing access to any one of the 256 words of memory. There are two types of write operations, ‘ ...
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... NXP Semiconductors slave address (memory) SDA START condition Fig 12. Byte write 7.4.1.2 Page write A page write is initiated in the same way as the byte write, if after sending the first word of data the STOP condition is not received, the PCA9501 considers subsequent words as data. After each data word the PCA9501 responds with an acknowledge and the four least signifi ...
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... NXP Semiconductors Fig 14. Current address read 7.4.2.2 Random read The PCA9501’s random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read. The master must perform a byte write to the address location to be ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 19. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Application design-in information A central processor/controller typically located on the system main board can use the 400 kHz I status or version control type of information. The PCA9501 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data, and so on. Alternately, these devices can be used as convenient interface for board confi ...
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... NXP Semiconductors MASTER CONTROLLER SCL SDA INT V SS GPIO device address configured as 0110 000x for this example. EEPROM device address configured as 1110 000x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used and must be configured as outputs. ...
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... NXP Semiconductors 11. Static characteristics Table 5. Static characteristics +85 C; unless otherwise specified. DD amb Symbol Parameter Supply V supply voltage DD I standby current DDQ I supply current read DD1 I supply current write DD2 V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage ...
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... NXP Semiconductors 2 2 3 3.6 V 100 160 0 1 amb amb Fig 23. V versus Remark: Rapid fall-off in V overvoltage protection for the GPIO I/O pins. When the GPIO I/Os are being used as inputs, the internal current source V resistors are required to provide sufficient V ...
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... NXP Semiconductors 12. Dynamic characteristics Table 6. Dynamic characteristics Symbol Parameter 2 [1] I C-bus timing (see Figure 24) f SCL clock frequency SCL t pulse width of spikes that must be SP suppressed by the input filter t bus free time between a STOP and START BUF condition t set-up time for a repeated START condition SU ...
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... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA 2 Fig 24. I C-bus timing SCL th SDA 8 bit word n Fig 25. Write cycle timing PCA9501_4 Product data sheet 2 8-bit I C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM bit 7 bit 6 MSB (A6) ...
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... NXP Semiconductors 13. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 0.85 mm terminal 1 index area terminal 1 20 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 10. Acronym ASIC CBT CDM CPU EEPROM ESD GPIO HBM 2 I C-bus I/O ...
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... PCA9501_4 20090210 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 1 “General address starts with ‘1’ and the fixed EEPROM I address starts with ‘ ...
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... NXP Semiconductors Table 11. Revision history …continued Document ID Release date • Modifications: added (continued) • updated soldering information PCA9501_3 20040930 (9397 750 14135) PCA9501_2 20030912 (9397 750 12058) PCA9501_1 20020927 (9397 750 10327) PCA9501_4 Product data sheet 2 8-bit I C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM Data sheet status Section 15 “ ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 I/O operations . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3.1 Quasi-bidirectional I/ 7.3.2 Interrupt ...