PCF8575TS/1,118 NXP Semiconductors, PCF8575TS/1,118 Datasheet - Page 15

• Manufacturer Part Number: PCF8575TS/1,118
• Description: IC I/O EXPANDER I2C 16B 24SSOP
• Manufacturer: NXP Semiconductors

Specifications of PCF8575TS/1,118

• Package / Case: 24-SSOP
• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCF8575
• Operating Supply Voltage: 2.5 V to 5.5 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Current: 25 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1079-2; 935276552118; PCF8575TSDB-T

Philips Semiconductors
11 I
See Fig.13 and note 1.
Notes
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of widths less than t
3. The rise and fall times specified here refer to the driver device (PCF8575) and are part of the general fast I
1999 Apr 07
handbook, full pagewidth
f
t
t
t
t
t
t
t
t
t
t
t
C
SCL
SW
BUF
SU;STA
HD;STA
LOW
HIGH
r
f
SU;DAT
HD;DAT
SU;STO
SYMBOL
b
Remote 16-bit I/O expander for I
PROTOCOL
SDA
and V
specification when PCF8575 asserts an acknowledge on SDA, the minimum fall time is 20 ns + 0.1C
SCL
2
C-BUS TIMING CHARACTERISTICS
IH
with an input voltage swing of V
SCL clock frequency
tolerable spike width on bus
BUS free time between a STOP
and START condition
START condition set-up time
START condition hold time
SCL LOW time
SCL HIGH time
SCL and SDA rise time
SCL and SDA fall time
data set-up time
data hold time
STOP condition set-up time
capacitive load represented by
each bus line
t SU;STA
t BUF
CONDITION
START
(S)
t HD;STA
PARAMETER
t LOW
t r
BIT 7
MSB
(A7)
t HIGH
Fig.13 I
SS
to V
t SU;DAT
t f
note 2
note 3
note 3
DD
2
2
1/f SCL
C-bus
C-bus timing diagram.
BIT 6
.
(A6)
CONDITIONS
15
t HD;DAT
(R/W)
BIT 0
LSB
1.3
0.6
0.6
1.3
0.6
20 + 0.1C
20 + 0.1C
100
0
0.6
ACKNOWLEDGE
MIN.
b
b
(A)
400
50
300
300
400
Product specification
MAX.
CONDITION
STOP
PCF8575
(P)
t SU;STO
b
.
SW(max)
MGL546
kHz
ns
ns
ns
ns
ns
pF
2
UNIT
s
s
s
s
s
s
C-bus
.
IL