LMH0071SQ/NOPB National Semiconductor, LMH0071SQ/NOPB Datasheet - Page 11

• Manufacturer Part Number: LMH0071SQ/NOPB
• Description: IC DESERIAL SDI W/LVDS 48LLP
• Manufacturer: National Semiconductor
• Series: LMH®r

Specifications of LMH0071SQ/NOPB

• Function: Deserializer
• Data Rate: 3Gbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 2
• Number Of Outputs: 5
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH0071SQ

Functional Description
DEVICE OPERATION
The DES is used in digital video signal origination equipment.
It is intended to be operated in conjunction with an FPGA host
which processes data received by the SER, and converts the
five bit output data to an appropriate parallel video format —
usually 10 or 20 bits wide. In most applications, the input data
to the DES will be data compliant with DVB ASI, SMPTE
259M-C, SMPTE 292M or SMPTE 424M, and the decoding
will be done by the IP provided by National Semiconductor or
similar IP to result in a decoded output. National Semicon-
ductor offers IP in source code format to perform the appro-
priate decoding of the data, as well as evaluation platforms to
assist in the development of target applications. For more in-
formation please contact your local National Semiconductor
Sales Office/Distributor
POWER SUPPLIES
The DES has several power supply pins, at 2.5V as well as
3.3V. It is important that these pins all be connected, and
properly bypassed. Bypassing should consist of parallel
4.7μF and 0.1μF capacitors as a minimum, with a 0.1μF ca-
pacitor on each power pin. The device has a large contact in
the center of the bottom of the package. This contact must be
connected to the system GND as it is the major ground con-
nection for the device. A 22 μF capacitor is required on the
V
Discrete bypassing is ineffective above 30 MHz to 50 MHz in
power plane-based distribution systems. Above this frequen-
cy range, the intrinsic capacitance of the power-ground sys-
tem can be used to provide additional RF bypassing. To make
the best use of this, make certain that there are PCB layers
dedicated to the Power supplies and to GND, and that they
are placed next to each other to provide a distributed capac-
itance between power and GND.
The DES will work best when powered from linear regulators.
The output of linear regulators is generally cleaner with less
noise than switching regulators. Output filtering and power
system frequency compensation are generally simpler and
more effective with linear regulators. Low dropout linear reg-
ulators are available which can usually operate from lower
input voltages such as logic power supplies, thereby reducing
regulator power dissipation. Cascading of low dropout regu-
lators should not be done since this places the entire supply
current load of both load systems on the first regulator in the
cascade and increases its loading and thermal output.
POWER UP
The 3.3V power supply should be brought up before the 2.5V
supply. The timing of the supply sequencing is not important.
The device has a power on reset sequence which takes place
once both power supplies are brought up. This sequence will
reset all register contents to their default values, and will place
the PLLs into link acquisition mode, attempting to lock on the
RXIN
RESET
There are three ways in which the device may be reset. There
is an automatic reset which happens on power-up; there is a
reset pin, which when brought low will reset the device, with
normal operation resuming when the pin is driven high again.
The third way to reset the device is a soft reset, implemented
via a write to the reset register. This reset will put all of the
register values back to their default values, except it will not
DDPLL
0
input.
pin which is connected to the 3.3V rail
11
affect the address register value if the SMBus default address
has been changed.
LVDS OUTPUTS
The DES has LVDS outputs, compatible with ANSI/TIA/
EIA-644. LVDS outputs expect to drive a 100Ω transmission
line which is properly terminated at the host FPGA inputs. It
is recommended that the PCB trace between the FPGA and
the receiver be less than 25 cm. Longer PCB traces may in-
troduce signal degradation as well as channel skew which
could cause serialization errors.
The LVDS outputs on the DES have a programmable output
swing. The default condition is for the smaller size swing, in
order to save power. If a larger amplitude output swing is de-
sired, this can be effected through the use of register 0x27h
LVDS OUTPUT TIMING
The DES output timing, in it's default condition, is described
in the LVDS Switching characteristics table. The user has the
ability to adjust the LVDS output timing to make it easier to
latch into the host FPGA if desired. This is done via register
0x28h where both the clock to data timing may be adjusted,
as well as changing the RXCLK from being a DDR clock to a
clock at the rate of DDR/2
LOOP FILTER
The DES has an internal PLL which is used to recover the
embedded clock from the input data. The loop filter for this
PLL has external components, and for optimum results in
Serial Digital Interface applications, a capacitor and a resistor
in series should be connected between pins 26 and 27 as
shown in the typical interface circuit.
DVB-ASI MODE
DVB-ASI mode is enabled when the DVB-ASI pin is brought
to a high state. When the DVB-ASI mode is enabled, an in-
ternal framer and 8b10b decoder is engaged such that the
data appearing on RX0-RX3 will represent a nibble of the de-
coded 8b10b data. RX4 is an Idle character detect and can
be used as an enable to allow the receiver to not write data
into an external FIFO. RX4 is high if the data being presented
on RX0-RX3 represents the idle character. The Least Signif-
icant Nibble of data is presented on the rising edge of RXCLK,
and the most significant on the falling edge of RXCLK.
The internal 8b10b decoder needs to receive up to 110 con-
secutive K28.5 characters to properly initialize and frame the
data so that the decoded 8b10b data presented at the output
of the device is correct.
SDI INPUT INTERFACING
The device has two inputs, one of which is selected via a
multiplexer with the RX_MUX_SEL pin. Whichever input is
selected will be routed to the clock recovery portion of the
deserializer, and once it is reclocked, the signal will be fed to
the loopthrough outputs. Most SDI interfaces require an
equalizer to meet performance requirements. For HD-SDI
and SD-SDI applications, the LMH0044 is an ideal equalizer
to use for this. The LMH0044 is packaged in a small compact
package and the outputs can be connected directly to the
RXIN inputs of the LMH0041. The LMH0344 is pin compatible
with the LMH0044 and will support 3 Gbps data, making it an
ideal choice to accompany the LMH0341.
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