LMH0071SQ/NOPB National Semiconductor, LMH0071SQ/NOPB Datasheet - Page 16

• Manufacturer Part Number: LMH0071SQ/NOPB
• Description: IC DESERIAL SDI W/LVDS 48LLP
• Manufacturer: National Semiconductor
• Series: LMH®r

Specifications of LMH0071SQ/NOPB

• Function: Deserializer
• Data Rate: 3Gbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 2
• Number Of Outputs: 5
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH0071SQ

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Application Information
PCB LAYOUT RECOMMENDATIONS
In almost all applications, the inputs to the DES will be driven
by the output of an equalizer such as the LMH0044. You
should follow the recommendations on the equalizer
datasheet for the interface between the input connector and
the equalizer—the DES will be placed between the equalizer
and the FPGA. If the DES is too close to the equalizer, then
there is a risk of crosstalk between the high speed digital out-
puts of the DES and the equalizer inputs. Conversely, if too
far away then the interconnect between the equalizer and the
DES may either pick up stray noise, or may broadcast noise
since this is a very high speed signal. Be certain to treat the
signal from the equalizer to the DES as a differential trace. If
there is skew between the two conductors of the differential
trace, not only might this cause difficulties for the DES receive
circuitry, but having a phase difference between the sides of
the pair makes the signal look and radiate like a common
mode signal.
If the loopthrough output is going to be used, it is advised that
the DES be placed close to the Loopthrough output BNC con-
nector, and the equalizer be placed close to the SDI Input
BNC connector. This will minimize the lengths of the most
critical connections.
The DES includes a cable driver for the loopthrough output.
The SMPTE Serial specifications have very stringent require-
ments for output return loss on drivers. The output return loss
will be degraded by non-idealities in the connection between
the DES and the output connector. All efforts should be taken
to minimize the trace lengths for this area, and to assure that
the characteristic impedance of this trace is 75Ω. The 75Ω
termination resistor should be placed as close to the
loopthrough output pin as is practicable.
It is recommended that the PCB traces between the host
FPGA and the DES be no longer than 10 inches (25cm) and
that the traces be routed as differential pairs, with very tight
matching of line lengths and coupling within a pair, as well as
equal length traces for each of the six pairs.
PCB DESIGN DO’S AND DON’TS
DO Whenever possible dedicate an entire layer to each power
supply whenever possible—this will reduce the inductance in
the supply plane.
DO use surface mount components whenever possible.
DO place bypass capacitors close to each power pin.
DON’T create ground loops—pay attention to the cutouts that
are made in your power and ground planes to make sure that
there are not opportunities for loops.
DON’T allow discontinuities in the ground planes—return cur-
rents will follow the path of least resistance—for high fre-
quency signals this will be the path of least inductance.
DO place the Loopthrough outputs as close as possible to the
edge of the PCB where it will connect to the outside world.
DO make sure to match the trace lengths of all differential
traces, both between the sides of an individual pair, and from
pair to pair.
DO remember that VIAs have significant inductance—when
using a via to connect to a power supply or ground layer, two
in parallel are better than one.
DO connect the slug on the bottom of the package to a solid
Ground connection. This contact is used for the major GND
connection to the device as well as serving as a thermal via
to keep the die at a low operating temperature.
16
TYPICAL SMPTE APPLICATIONS CIRCUIT
A typical application circuit for the DES is shown in
15. This circuit shows the LMH0341 3 Gbps deserializer, al-
ternately this could employ the LMH0041 or LMH0071 dese-
rializers in lower data rate SMPTE applications.
The RX interface between the DES and the host FPGA is
composed of a 5-bit LVDS Data bus and its LVDS clock. This
is a point-to-point interface. Line termination should be pro-
vided by the FPGA device. If not, and external 100Ω resistor
maybe used and should be located as close to the FPGA as
possible to minimize stub lengths. Pairs should be of equal
length to minimize any skew impact. The LVDS clock (RX-
CLK) uses both edges to transfer the data.
An SMBus is also connected from the host FPGA to the DES.
If the SMBus is shared, a chip select signal is used to select
the device being addressed. The SCK and SDA signals re-
quire a pull up resistor. The SMB_CS is driven by a GPO
signal from the FPGA. Depending on the FPGA I/O it may also
require a pull up unless it is a push / pull output.
Depending upon the application, several other Host GPIO
signals maybe used. This includes the DVB_ASI and RE-
SET input signals. If these pins are not used, then must be
tied off to the desired state. The LOCK signal maybe used to
monitor the DES. If it is unused, leave the pin as a NC (or
route to a test point).
Note also in this circuit, the LMH0341 GPIO_1 pin has been
configured to provide the status of RXIN_1. When there is a
signal present coming from the LMH0340, then RXIN_1 will
be selected. If that signal is lost, the input MUX will automat-
ically switch over to provide the system reference black signal
as the input from RXIN_0.
The DES includes a SMPTE compliant cable driver for the
Loopthrough function. While this is a differential driver, it is
commonly used single-endedly to drive 75 Ω coax cables.
External 75 Ω pull up resistors are used to the 2.5V rail. The
active output(s) also includes a matching network to meet the
required Output Return Loss SMPTE specification. While ap-
plication specific, in general a series 75 Ω resistor shunted by
a 6.8 nH inductor will provide a starting value to design with.
The signal is then AC coupled to the cable with a 4.7 µF ca-
pacitor. If the complementary output is not used, simply ter-
minate it after its AC coupling capacitor to ground. This output
(even though its inverting) may still be used for a loop back
or 1:2 function due to the nature of the NRZI coding that the
FIGURE 14. Evaluation Board Loopthrough Output
Return Loss
30017219
Figure