IC I2C BUS REPEATER 8-SOIC

PCA9515AD,118

Manufacturer Part NumberPCA9515AD,118
DescriptionIC I2C BUS REPEATER 8-SOIC
ManufacturerNXP Semiconductors
TypeRepeater
PCA9515AD,118 datasheet
 


Specifications of PCA9515AD,118

Package / Case8-SOIC (3.9mm Width)Tx/rx TypeI²C Logic
Delay Time113nsCapacitance - Input6pF
Voltage - Supply2.3 V ~ 3.6 VCurrent - Supply800µA
Mounting TypeSurface MountLogic FamilyPCA9515A
Operating Supply Voltage2.3 V to 3.6 VPower Dissipation100 mW
Operating Temperature Range- 40 C to + 85 CInput Voltage5.5 V
Logic TypeI2C BusMaximum Clock Frequency400 KHz
Mounting StyleSMD/SMTOutput Current50 mA
Output Voltage5.5 VLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use WithOM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2COther names568-1031-2
935276766118
PCA9515AD-T
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PCA9515A
2
I
C-bus repeater
Rev. 04 — 11 April 2008
1. General description
The PCA9515A is a CMOS integrated circuit intended for application in I
SMBus systems.
While retaining all the operating modes and features of the I
extension of the I
enabling two buses of 400 pF.
2
The I
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515A enables the system designer to isolate two halves of a bus, thus
more devices or longer length can be accommodated. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the
100 kHz bus is isolated when 400 kHz operation of the other is required.
Two or more PCA9515As cannot be put in series. The PCA9515A design does not
allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output. A ‘regular
LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a
slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,
PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A
will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.
The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in
series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with
themselves since they use shifting instead of static offsets to avoid lock-up conditions.
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
2. Features
I
2-channel, bidirectional buffer
I
2
I
C-bus and SMBus compatible
I
Active HIGH repeater enable input
I
Open-drain input/outputs
I
Lock-up free operation
I
Supports arbitration and clock stretching across the repeater
I
Accommodates Standard-mode and Fast-mode I
I
Powered-off high-impedance I
I
Operating supply voltage range of 2.3 V to 3.6 V
I
5.5 V tolerant I
2
C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
2
C-bus pins
2
C-bus and enable pins
Product data sheet
2
C-bus and
2
C-bus system, it permits
2
C-bus devices and multiple masters

PCA9515AD,118 Summary of contents

  • Page 1

    PCA9515A 2 I C-bus repeater Rev. 04 — 11 April 2008 1. General description The PCA9515A is a CMOS integrated circuit intended for application in I SMBus systems. While retaining all the operating modes and features of the I extension ...

  • Page 2

    ... NXP Semiconductors 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater) I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ...

  • Page 3

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol n.c. SCL0 SDA0 GND EN SDA1 SCL1 V CC PCA9515A_4 Product data sheet SCL0 SCL1 PCA9515AD SDA0 3 6 SDA1 GND 002aad736 Pin configuration for SO8 Pin description Pin Description ...

  • Page 4

    ... NXP Semiconductors 6. Functional description Refer to The PCA9515A integrated circuit contains two identical buffer circuits which enable 2 I C-bus and similar bus systems to be extended without degradation of system performance. The PCA9515A contains two bidirectional, open-drain buffers specifically designed to support the standard LOW-level contention arbitration of the I arbitration or clock stretching, the PCA9515A acts like a pair of non-inverting, open-drain buffers, one for SDA and one for SCL ...

  • Page 5

    ... NXP Semiconductors 7. Application design-in information A typical application is shown 3 unless the slave bus is isolated and then the master bus can run at 400 kHz. Master devices can be placed on either bus. Fig 4. The PCA9515A tolerant does not require any additional circuitry to translate between the different bus voltages. ...

  • Page 6

    ... NXP Semiconductors SCL SDA V of master OL Fig 5. Bus 0 waveform SCL SDA Fig 6. Bus 1 waveform 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND. Symbol Parameter V supply voltage voltage on I C-bus, SCL or SDA ...

  • Page 7

    ... NXP Semiconductors 9. Static characteristics Table 4. Static characteristics ( GND = Symbol Parameter Supplies V supply voltage CC I HIGH-level supply current CCH I LOW-level supply current CCL I contention LOW-level supply current CCLc Input SCLn; input/output SDAn V HIGH-level input voltage IH V LOW-level input voltage IL V contention LOW-level input voltage ...

  • Page 8

    ... NXP Semiconductors Table 5. Static characteristics ( GND = Symbol Parameter Supplies V supply voltage CC I HIGH-level supply current CCH I LOW-level supply current CCL I contention LOW-level supply current CCLc Input SCLn; input/output SDAn V HIGH-level input voltage IH V LOW-level input voltage IL V contention LOW-level input voltage ...

  • Page 9

    ... NXP Semiconductors 10. Dynamic characteristics Table 6. Dynamic characteristics ( 2 2.7 V; GND = Symbol Parameter t HIGH-to-LOW propagation delay PHL t LOW-to-HIGH propagation delay PLH t HIGH to LOW output transition time THL t LOW to HIGH output transition time TLH t set-up time su t hold time h [1] Typical values taken 2.5 V and T ...

  • Page 10

    ... NXP Semiconductors 11. Test information Fig 8. PCA9515A_4 Product data sheet PULSE GENERATOR R = load resistor; 1. load capacitance includes jig and probe capacitance termination resistance should be equal Test circuit for open-drain outputs Rev. 04 — 11 April 2008 PCA9515A DUT 002aad479 of pulse generators C-bus repeater © NXP B.V. 2008. All rights reserved. ...

  • Page 11

    ... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 12

    ... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

  • Page 13

    ... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 14

    ... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

  • Page 15

    ... NXP Semiconductors Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 10. Acronym CDM CMOS ESD HBM 2 I C-bus MM SMBus PCA9515A_4 Product data sheet ...

  • Page 16

    ... Release date PCA9515A_4 20080411 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 1 “General • Table 2 “Pin – ...

  • Page 17

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 18

    ... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Enable 6.2 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Application design-in information . . . . . . . . . . 5 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.1 AC waveforms ...