P82B715TD,112 NXP Semiconductors, P82B715TD,112 Datasheet - Page 14

• Manufacturer Part Number: P82B715TD,112
• Description: IC I2C BUS EXTENDER 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Bus Extenderr

Specifications of P82B715TD,112

• Package / Case: 8-SOIC (3.9mm Width)
• Tx/rx Type: I²C Logic
• Delay Time: 250ns
• Capacitance - Input: 3000pF
• Voltage - Supply: 4.5 V ~ 12 V
• Current - Supply: 22mA
• Mounting Type: Surface Mount
• Logic Family: P82B
• Number Of Lines (input / Output): 1 / 1
• Propagation Delay Time: 250 ns
• Operating Supply Voltage: 4.5 V to 12 V
• Power Dissipation: 300 mW
• Operating Temperature Range: - 40 C to + 85 C
• Logic Type: I2C Bus Extender
• Mounting Style: SMD/SMT
• Number Of Input Lines: 1
• Number Of Output Lines: 1
• Output Current: 60 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3981-5; 935154770112; P82B715TD; P82B715TD

NXP Semiconductors
Table 5.
T
[1]
[2]
[3]
[4]
11. Test information
P82B715_8
Product data sheet
Symbol
Input currents
I
I
I
Impedance transformation
Z
Buffer delay times
t
I
I
t
V
V
Sx
Lx
Lx
rise/fall delay
Sx
Sy
rise/fall delay
amb
Fig 12. Test circuit for delay times
in
Lx
Ly
, I
, I
, I
/Z
to V
to V
to V
to V
Operation with reduced performance is possible down to 3 V. Typical static sinking performance is not degraded at 3 V, but the dynamic
sink currents while the output is being driven through 0.5V
accommodate the guaranteed minimums.
Buffer is passive in this test. The Sx/Sy sink current flows via an internal resistor to the driver connected at the Lx/Ly I/O.
A conventional input-output delay will not be observed in the Sx/Lx voltage waveforms because the input and output pins are internally
tied with a 30
input pin cannot rise/fall until the buffered bus load at the output pin has been driven by the internal amplifier. This test measures the bus
propagation delay caused to falling or rising voltages at the Lx/Ly output (as well as the Sx/Sy input) by the amplifier’s response time.
The figure given is measured with a drive current as shown in
bus driving IC has an output voltage well above 0.4 V, 6 mA is used instead of the static 3 mA.
The signal path Lx to Sx and Ly to Sy is passive via the internal 30
propagation delay.
Ly
Ly
Sy
out
= 25 C; V
Lx
Ly
5 V
Sx
Sy
I = 6 mA
input
Characteristics
Parameter
input current from I
input current from buffered bus
leakage current on buffered bus V
input/output impedance
time delay to V
crossing 0.5V
current step I
buffer time delay of switching
edges between V
V
Sx
CC
4.7 k
V
output
Sx
= 5 V; unless otherwise specified.
resistor so they show equal logic voltage levels, to within 100 mV. When connected in an I
P82B715
Sx
CC
Lx
at Sx
…continued
for input drive
voltage
Lx
2
C-bus
input and
Lx
V
270
Lx
Conditions
I
V
I
V
V
I
see
no capacitive load; V
R
no capacitive load; V
Lx
2
Lx
CC
C-bus = 3 mA
CC
Sx
Sx
Sx
Rev. 08 — 9 November 2009
, I
P82B715
sinking 30 mA on buffered bus
, V
< V
Figure
pull-up = 4700 ;
Ly
> 3 V; I
= 3 V to 12 V; V
Sy
sink on buffered bus = 30 mA
Lx
= V
CC
and the buffer is active;
12; R
Sx
are reduced and can increase fall times. Timing-critical designs should
CC
Figure
, I
Sx
Sy
Lx
output
sink on
12. Because this is a dynamic bus test in which a corresponding
pull-up = 270 ;
resistor. There is no amplifier involved and essentially no signal
Lx
CC
CC
, V
4.7 k
= 5 V
= 5 V
V
Ly
= V
CC
current
input
input and
and
voltage
output
[2]
[3]
[4]
t
delay
Min
-
-
-
8
-
-
2
C-bus system, an Sx/Sy
Typ
-
-
-
10
250
0
P82B715
© NXP B.V. 2009. All rights reserved.
I
t
delay
2
C-bus extender
Max
200
13
-
-
3
3
002aad693
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Unit
mA
mA
ns
ns
5 V
0 V
A