PCA9545APW,112 NXP Semiconductors, PCA9545APW,112 Datasheet - Page 11

• Manufacturer Part Number: PCA9545APW,112
• Description: IC I2C SWITCH 4CH 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9545APW,112

• Package / Case: 20-TSSOP
• Applications: 4-Channel I²C Switcher
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Number Of Channels: 4 Channel
• On Resistance (max): 55 Ohms
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Supply Current: 100 mA
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Switches: 1
• Off State Leakage Current (max): 1 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935275809112; PCA9545APW; PCA9545APW

NXP Semiconductors
PCA9545A_45B_45C_7
Product data sheet
Fig 12. System configuration
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
7.3 System configuration
7.4 Acknowledge
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 13. Acknowledgement on the I
RECEIVER
SLAVE
SCL from master
by transmitter
data output
by receiver
data output
TRANSMITTER/
Rev. 07 — 19 June 2009
RECEIVER
condition
START
SLAVE
S
4-channel I
Figure
2
C-bus
TRANSMITTER
1
12).
MASTER
2
C-bus switch with interrupt logic and reset
PCA9545A/45B/45C
2
TRANSMITTER/
RECEIVER
MASTER
acknowledgement
not acknowledge
SLAVE
clock pulse for
acknowledge
8
MULTIPLEXER
© NXP B.V. 2009. All rights reserved.
002aaa987
I
2
9
C-BUS
002aaa966
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